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Computer Specification Instruction Set Architecture (ISA) - the specification of a computer's appearance to a programmer at its lowest level Computer Architecture - a high-level description of the hardware implementing the computer derived from the ISA

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10-1

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  1. Henry Hexmoor

  2. Computer Specification Instruction Set Architecture (ISA) - the specification of a computer's appearance to a programmer at its lowest level Computer Architecture - a high-level description of the hardware implementing the computer derived from the ISA The architecture usually includes additional specifications such as speed, cost, and reliability. 10-1 Henry Hexmoor

  3. Simple computer architecture decomposed into: Datapath for performing operations Control unit for controlling datapath operations A datapath is specified by: A set of registers The microoperations performed on the data stored in the registers A control interface Introduction (continued) Henry Hexmoor

  4. Guiding principles for basic datapaths: The set of registers Collection of individual registers A set of registers with common access resources called a register file A combination of the above Microoperation implementation One or more shared resources for implementing microoperations Buses - shared transfer paths Arithmetic-Logic Unit (ALU) - shared resource for implementing arithmetic and logic microoperations Shifter - shared resource for implementing shift microoperations Datapaths10-2 Henry Hexmoor

  5. Four parallel-loadregisters (R0-R3) Two mux-based register selectors Register destination decoder Mux B for external constant input Buses A and B with externaladdress and data outputs ALU and Shifter withMux F for output select Mux D for external data input Logic for generating status bitsV, C, N, Z Datapath ExampleFigure 10-1 Load enable A select B select Write A address B address n D data Load R0 2 2 n n Load R1 0 n 1 MUX 2 n 3 0 1 MUX Load 2 R2 3 n n Load R3 n n 0 1 2 3 n Register file Decoder A data B data D address n n 2 Constant in Destination select n 1 0 MB select MUX B Address n Bus A Out n Bus B Data A B Out n G select H select B A B 4 2 S S || C 2:0 in I I 0 0 V Shifter Arithmetic/logic R L unit (ALU) C H G N n n Zero Detect Z 0 1 MF select Function unit MUX F F Data In n n Henry Hexmoor 0 1 MD select MUX D Bus D n

  6. Microoperation: R0 ← R1 + R2 Load enable A select B select Write A address B address n D data • Apply 01 to A select to place contents of R1 onto Bus A Load R0 2 2 n n Load R1 0 n 1 MUX 2 n 3 0 1 MUX Load 2 R2 • Apply 0010 to G select to perform addition G = Bus A + Bus B 3 n n Load R3 • Apply 0 to MF select and 0 to MDselect to place the value of G onto BUS D n n 0 1 2 3 n Register file Decoder A data B data D address n n 2 Constant in Destination select n 1 0 MB select • Apply 00 to Destination select to enable the Load input to R0 MUX B Address n Bus A Out n Bus B Data A B Out n G select H select • Apply 1 to Load Enable to force the Load input to R0 to 1 so that R0 is loaded on the clock pulse (not shown) • The overall microoperation requires1 clock cycle B A B 4 2 S S || C 2:0 in I I 0 0 V Shifter Arithmetic/logic R L unit (ALU) C H G N n n Zero Detect Z 0 1 MF select Function unit MUX F F Data In n n 0 1 MD select MUX D Bus D n Datapath Example: Performing a Microoperation • Apply 10 to B select to place contents of R2 onto B data and apply 0 to MB select to place B data on Bus B Henry Hexmoor

  7. In this and the next section, we deal with detailed design of typical ALUs and shifters Decompose the ALU into: An arithmetic circuit A logic circuit A selector to pick between the two circuits Arithmetic circuit design Decompose the arithmetic circuit into: An n-bit parallel adder A block of logic that selects four choices for the B input to the adder See next slide for diagram Arithmetic Logic Unit (ALU) Henry Hexmoor

  8. There are only four functions of B to select as Y in G = A + Y: All 0’s B B All 1’s G = A + B G = A + B + 1 Arithmetic Circuit DesignFigure 10-3 and Table 10-1 and table 10-2 (pages 435, 438) Cin = 0 Cin = 1 G = A G = A + 1 G = A + B G = A + B + 1 Subtraction G = A – 1 G = A C in n X A n-bit n n G = X Y + Cin parallel B adder n B input Y logic S 0 S 1 Henry Hexmoor C out

  9. The text gives a circuit implemented using a multiplexer plus gates implementing: AND, OR, XOR and NOT Here we custom design a circuit for bit Gi by beginning with a truth table organized as logic operation K-map and assigning (S1, S0) codes to AND, OR, etc. Gi = S0 Ai Bi + S1 Ai Bi+S0 Ai Bi + S1 S0 Ai Gate input count forMUX solution > 29 Gate input count forabove circuit < 20 Custom design better Logic Circuit Henry Hexmoor

  10. The custom circuit has interchanged the (S1,S0) codes for XOR and NOT compared to the MUX circuit. To preserve compatibility with the text, we use the MUX solution. Next, use the arithmetic circuit, the logic circuit, and a 2-way multiplexer to form the ALU. See the next slide for the bit slice diagram. The input connections to the arithmetic circuit and logic circuit have been been assigned to prepare for seamless addition of the shifter, keeping the selection codes for the combined ALU and the shifter at 4 bits: Carry-in Ci and Carry-out Ci+1 go between bits Ai and Bi are connected to both units A new signal S2 performs the arithmetic/logic selection The select signal entering the LSB of the arithmetic circuit, Cin, is connected to the least significant selection input for the logic circuit, S0. Arithmetic Logic Unit (ALU) Henry Hexmoor

  11. The next most significant select signals, S0 for the arithmetic circuit and S1 for the logic circuit, are wired together, completing the two select signals for the logic circuit. The remaining S1 completes the three select signals for the arithmetic circuit. C C C C in i i i 1 + A A i i One stage of B B arithmetic i i circuit 2-to-1 S S 0 0 0 MUX S S 1 1 G i 1 S A i B One stage of i logic circuit S 0 S 1 S 2 Arithmetic Logic Unit (ALU)Figure 10-7 Henry Hexmoor

  12. Direction: Left, Right Number of positions with examples: Single bit: 1 position 0 and 1 positions Multiple bit: 1 to n – 1 positions 0 to n – 1 positions Filling of vacant positions Many options depending on instruction set Here, will provide input lines or zero fill Combinational Shifter Parameters10-4 Henry Hexmoor

  13. Serial Inputs: IR for right shift IL for left shift Serial Outputs R for right shift (Same as MSB input) L for left shift (Same as LSB input) B B B B 3 2 1 0 Serial output L Serial output R I I R L M M M M 0 1 2 0 1 2 0 1 2 0 1 2 S S S S U U U U X X X X 2 S H H H H 3 2 1 0 4-Bit Basic Left/Right Shifter (Figure 10-8) • Shift Functions:(S1, S0) = 00 Pass B unchanged 01 Right shift 10 Left shift 11 Unused Henry Hexmoor

  14. A rotate is a shift in which the bits shifted out are inserted into the positions vacated The circuit rotates its contents left from 0 to 3 positions depending on S:S = 00 position unchanged S = 10 rotate left by 2 positionsS = 01 rotate left by 1 positions S = 11 rotate left by 3 positions See Table 10-3 in text for details (page 440) D D D D 3 2 1 0 S 0 S 1 3 2 1 0 S S 3 2 1 0 S S 3 2 1 0 S S 3 2 1 0 S S 1 0 1 0 1 0 1 0 M M M M U U U U X X X X Y Y Y Y 3 2 1 0 Barrel Shifter(Figure 10-9) Henry Hexmoor

  15. Large barrel shifters can be constructed by using: Layers of multiplexers - Example 64-bit: Layer 1 shifts by 0, 16, 32, 48 Layer 2 shifts by 0, 4, 8, 12 Layer 3 shifts by 0, 1, 2, 3 See example in section 12-2 of the text 2 dimensional array circuits designed at the electronic level Barrel Shifter (continued) Henry Hexmoor

  16. Here we move up one level in the hierarchy from that datapath The registers, and the multiplexer, decoder, and enable hardware for accessing them become a register file A register file is an array of fast registers The ALU, shifter, Mux F and status hardware become a function unit The remaining muxes and buses which handle data transfers are at the new level of the hierarchy n D data Write m D address m 2 n x Register file m m A address B address A data B data Constant in n n n 1 0 MB select MUX B n Bus A Address out Bus B n Data out A B 4 FS V Function C unit N Z F n n Data in 0 1 MD select MUX D Datapath Representation10-5 Henry Hexmoor

  17. In the register file: Multiplexer select inputs become A address and B address Decoder input becomes D address Multiplexer outputs become A data and B data Input data to the registers becomes D data Load enable becomes write The register file now appears like a memory based on clocked flip-flops (the clock is not shown) The function unit labeling is quite straightforward except for FS n D data Write m D address m 2 n x Register file m m A address B address A data B data Constant in n n n 1 0 MB select MUX B n Bus A Address out Bus B n Data out A B 4 FS V Function C unit N Z F n n Data in 0 1 MD select MUX D Datapath Representation (continued) Henry Hexmoor

  18. Boolean Equations: MF = F3 F2 Gi = Fi Hi = Fi MF G H FS(3:0) Select Select(3:0) Select(3:0) Micr ooperation ¬ 0000 0 0000 XX F A ¬ + 0001 0 0001 XX F A 1 + ¬ 0010 0 0010 XX F A B ¬ + + 0011 0 0011 XX F A B 1 + ¬ 0100 0 0100 XX F A B + ¬ + 0101 0 0101 XX F A B 1 ¬ - 0110 0 0110 XX F A 1 ¬ 0111 0 0111 XX F A ¬ Ù 1000 0 1 X 00 XX F A B ¬ Ú 1001 0 1 X 01 XX F A B ¬ Å 1010 0 1 X 10 XX F A B ¬ 1011 0 1 X 11 XX F A ¬ F B 1100 1 XXXX 00 ¬ F sr B 1101 1 XXXX 01 ¬ 1110 1 XXXX 10 F sl B Definition of Function Unit Select (FS) Codes(Table 10-4, page 443)) Select, Select, and G H MF in T of Codes FS Henry Hexmoor

  19. The datapath has many control inputs The signals driving these inputs can be defined and organized into a control word To execute a microinstruction, we apply control word values for a clock cycle. For most microoperations, the positive edge of the clock cycle is needed to perform the register load The datapath control word format and the field definitions are shown on the next slide The Control Word Henry Hexmoor

  20. Fields DA – D Address (destination) AA – A Address BA – B Address (source for MUXB MB – Mux B (constant/source FS – Function Select MD – Mux D RW – Register Write The connections to datapath are shown in the next slide 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 M M R D A AA BA FS B D W Control word The Control Word Fields Henry Hexmoor

  21. n D data R W 0 Write 15 D A 14 D address 13 8 n x Register file 12 9 A address B address AA BA 11 8 7 10 A data B data n n n Constant in 1 0 6 MB MUX B Bus A n Address out Bus B n Data out A B V 5 Function C 4 FS unit N 3 Z 2 n n Data in 0 1 MD 1 MUX D Bus D Control Word Block Diagram (Figure 10-11) Henry Hexmoor

  22. Control Word EncodingTable 10-5 Encoding of Control W D A , AA, B A MB FS MD R W Function Code Function Code Function Code Function Code Function Code ¬ R 0 000 Register 0 F A 0000 Function 0 No write 0 R 1 001 Constant 1 0001 Data In 1 Write 1 ¬ + F A 1 ¬ + R 2 010 0010 F A B + + ¬ R 3 011 F A B 1 0011 + ¬ R 4 100 F A B 0100 + + ¬ R 5 101 0101 F A B 1 ¬ - R 6 110 F A 1 0110 ¬ R 7 111 F A 0111 ¬ Ù F A B 1000 ¬ Ú F A B 1001 1010 ¬ Å F A B 1011 ¬ F A 1100 ¬ F B ¬ 1101 F sr B 1110 ¬ F sl B Henry Hexmoor

  23. Microoperations for the Datapath - Symbolic RepresentationTable 10-6 Micr o- op eratio n D A A A B A M B F S M D R W ¬ R 1 R 2 R 3 R 1 R 2 R 3 R e g ister F A B 1 F unction Write – = + + ¬ R 4 s l R6 R 4 — R 6 R e g ister F sl B F unction Write = ¬ R 7 R 7 1 R 7 R 7 — Re gister Function Write F A 1 + = + ¬ R 1 R 0 2 R 1 R 0 — Con s tant Func tio n Write + F A B = + ¬ Data out R 3 —— R 3 R eg i s t e r — — N o Wr it e ¬ R 4 D ata in R 4 —— — — Data in Write ¬ Å R 5 0 R 5 R 0 R 0 R e g ister F A B F unction Write = Henry Hexmoor

  24. Results of simulation of the above on the next slide Micr o- o p eratio n D A A A B A M B F S M D R W ¬ 1 2 3 0 0 1 0 1 0 011 0 010 1 0 1 R R R – ¬ 4 s l R6 10 0 110 0 111 0 0 1 R XX X ¬ 7 7 1 11 1 1 11 0 000 1 0 1 R R XXX + ¬ 1 0 2 00 1 0 00 1 001 0 0 1 R R XXX + ¬ Data out 3 011 0 0 R XX X X XX XXX X X ¬ 4 D ata in 10 0 1 1 R XX X XXX X XXX X ¬ 5 0 1 0 1 0 0 0 000 0 101 0 0 1 R Microoperations for the Datapath - Binary RepresentationTable 10-7 m Microoperations from T a Binary C o o Henry Hexmoor

  25. clock 8 2 4 7 5 1 3 6 DA 1 4 7 1 0 4 5 AA 2 0 7 0 BA 3 6 0 3 0 FS 14 1 2 0 10 5 Constant_in X 2 X MB Address_out 2 0 7 0 3 6 0 2 3 0 Data_out 18 18 Data_in MD RW reg0 0 reg1 1 255 2 reg2 2 reg3 3 reg4 4 12 18 reg5 5 0 reg6 6 reg7 7 8 1 Status_bits 2 0 0 X Datapath SimulationFigure 10-12 Henry Hexmoor

  26. A programmable system uses a sequence of instructions to control its operation An typical instruction specifies: Operation to be performed Operands to use, and Where to place the result, or Which instruction to execute next Instructions are stored in RAM or ROM as a program The addresses for instructions in a computer are provided by a program counter (PC) that can Count up Load a new address based on an instruction and, optionally, status information Instruction Set Architecture (ISA) for Simple Computer (SC)10-7 Henry Hexmoor

  27. The PC and associated control logic are part of the Control Unit Executing an instruction - activating the necessary sequence of operations specified by the instruction Execution is controlled by the control unit and performed: In the datapath In the control unit In external hardware such as memory or input/output Instruction Set Architecture (ISA) (continued) Henry Hexmoor

  28. The storage resources are "visible" to the programmer at the lowest software level (typically, machine or assembly language) Storage resourcesfor the SC => Separate instruction anddata memories imply"Harvard architecture" Done to permit use ofsingle clock cycle perinstruction implementation Due to use of "cache" in modern computerarchitectures, is a fairlyrealistic model ISA: Storage ResourcesFigure 10-13 Program counter (PC) Instruction memory 15 x 2 16 Register file x 8 16 Data memory x 15 2 16 Henry Hexmoor

  29. A instruction consists of a bit vector The fields of an instruction are subvectors representing specific functions and having specific binary codes defined The format of an instruction defines the subvectors and their function An ISA usually contains multiple formats The SC ISA contains the three formats presented on the next slide ISA: Instruction Format Henry Hexmoor

  30. The three formats are: Register, Immediate, and Jump and Branch All formats contain an Opcode field in bits 9 through 15. The Opcode specifies the operation to be performed More details on each format are provided on the next three slides 15 9 8 6 5 3 2 0 Destination Source reg- Source reg- Opcode register (DR) ister A (SA) ister B (SB) (a) Register 15 9 8 6 5 3 2 0 Destination Source reg- Opcode Operand (OP) register (DR) ister A (SA) (b) Immediate 15 9 8 6 5 3 2 0 Address (AD) Address (AD) Source reg- Opcode (Left) (Right) ister A (SA) (c) Jump and Branch ISA: Instruction FormatFigure 10-14 Henry Hexmoor

  31. This format supports instructions represented by: R1 ← R2 + R3 R1 ← sl R2 There are three 3-bit register fields: DR - specifies destination register (R1 in the examples) SA - specifies the A source register (R2 in the first example) SB - specifies the B source register (R3 in the first example and R2 in the second example) 15 9 8 6 5 3 2 0 Destination Source reg- Source reg- Opcode register (DR) ister A (SA) ister B (SB) (a) Register ISA: Instruction Format (continued) Henry Hexmoor

  32. This format supports instructions described by: R1 ← R2 + 3 The B Source Register field is replaced by an Operand field OP which specifies a constant. The Operand: 3-bit constant Values from 0 to 7 The constant: Zero-fill (on the left of) the Operand to form 16-bit constant 16-bit representation for values 0 through 7 15 9 8 6 5 3 2 0 Destination Source reg- Opcode Operand (OP) register (DR) ister A (SA) (b) Immediate ISA: Instruction Format (continued) Henry Hexmoor

  33. This instruction supports changes in the sequence of instruction execution by adding an extended, 6-bit, signed 2s-complement address offset to the PC value The 6-bit Address (AD) field replaces the DR and SB fields Example: Suppose that a jump is specified by the Opcode and the PC contains 45 (0…0101101) and Address contains – 12 (110100). Then the new PC value will be:0…0101101 + (1…110100) = 0…0100001 (45 + (– 12) = 33) The SA field is retained to permit jumps and branches on N or Z based on the contents of Source register A 15 9 8 6 5 3 2 0 Address (AD) Address (AD) Source reg- Opcode (Left) (Right) ister A (SA) (c) Jump and Branch ISA: Instruction Format (continued) Henry Hexmoor

  34. The specifications provide: The name of the instruction The instruction's opcode A shorthand name for the opcode called a mnemonic A specification for the instruction format A register transfer description of the instruction, and A listing of the status bits that are meaningful during an instruction's execution (not used in the architectures defined in this chapter) ISA: Instruction Specifications Henry Hexmoor

  35. I n st ruction Speci fications for the Simple Comput er - Part 1 St a t u s Instr u ctio n O pc ode Mnem on ic Form a t D escrip tion Bits ¬ Move A 0000000 MO V A RD ,RA R [DR] R[SA ] N , Z ¬ Increment 0000001 INC R D , RA R[DR] R [ SA] + 1 N , Z ¬ Add 0000010 ADD R D , RA,RB R [DR] R[SA ] + R[ SB] N , Z ¬ - Subtr a ct 0000101 SUB R D , RA,RB R [DR] R[SA ] [ SB] N , Z R ¬ - D e crement 0000110 DEC R D , RA R[DR] R[SA ] 1 N , Z ¬ Ù AND 0001000 AND R D , RA,RB R [DR] R[SA ] R[SB ] N , Z ¬ Ú O R 0001001 OR RD ,RA,RB R[DR] R[SA ] R[SB ] N , Z ¬ Å Exclusive OR 0001010 XOR R D , RA,RB R [DR] R[SA ] R[SB] N , Z ¬ R[SA ] NO T 0001011 NO T R D , RA R[DR] N, Z ISA: Instruction Specifications (continued) Henry Hexmoor

  36. I n st ruction Speci fications for the Simple Comput er - Part 2 St a t u s Instr u ctio n O pc ode Mnem on ic Form a t D escrip tion Bits ¬ Move B 0001100 MO VB RD ,RB R [DR] R[SB] ¬ Shift Right 0001101 SHR R D , RB R[DR] sr R[SB] ¬ Shift Left 0001110 SHL R D , RB R[DR] sl R[SB] ¬ Load Imm e diate 1001100 LDI R D , O P R[DR] zf OP ¬ Add Immediate 1000010 ADI R D , RA,OP R [DR] R[SA] + zf OP ¬ Load 0010000 LD RD ,RA R [DR] M[ SA ] ¬ Store 0100000 ST RA,RB M [SA] R[SB] ¬ Branch on Zero 1100000 BRZ R A,AD if (R[ S A] = 0) PC PC + s e A D ¬ Branch on Negative 1100001 BRN R A,AD if (R[ S A] < 0) PC PC + s e A D ¬ J u mp 1110000 JMP R A P C R[SA ] ISA: Instruction Specifications (continued) Henry Hexmoor

  37. Memory Repr esentation of Instruc t ions and Data D eciimal Dec i mal Ad d r ess Mem o r y C ontents Op cod e Other F i elds Op eration ¬ - 25 00001 01 001 010 011 5 (Subtract) DR:1, SA:2, SB:3 R1 R2 R3 ¬ 35 01000 00 000 100 101 32 (Store ) S A:4, SB:5 M[ R4] R5 ¬ + 3 45 10000 10 010 111 011 66 (Add DR: 2 , S A : 7 , OP :3 R 2 R7 Im mediate) 55 11000 00 101 110 100 96 (Branch AD: 44, SA:6 If R6 = 0, ¬ - on Z e ro ) PC PC 20 70 000 000000110 00000 Data = 1 92. Aft e r execution of instruction in 35, Data = 8 0 . ISA:Example Instructions and Data in Memory Henry Hexmoor

  38. Based on the ISA defined, design a computer architecture to support the ISA The architecture is to fetch and execute each instruction in a single clock cycle The datapath from Figure 10-11 will be used The control unit will be defined as a part of the design The block diagram is shown on the next slide Single-Cycle Hardwired Control10-8 Henry Hexmoor

  39. IR(8:6) || IR(2:0) Extend V C Branch PC N Control Z Address B P J L B C Instruction memory RW D Register DA Instruction file AA BA A B Zero fill IR(2:0) Constant in Instruction decoder 0 1 MB MUX B Address out Bus A Bus B Data out MW D B A M F M R M P J B A A A S W W L C B D B A B Data in Address FS CONTROL V Data Function C memory unit Figure 10-15 N Data out Z F Data in 0 1 MD MUX D Bus D Henry Hexmoor DATAPATH

  40. The Data Memory has been attached to the Address Out and Data Out and Data In lines of the Datapath. The MW input to the Data Memory is the Memory Write signal from the Control Unit. For convenience, the Instruction Memory, which is not usually a part of the Control Unit is shown within it. The Instruction Memory address input is provided by the PC and its instruction output feeds the Instruction Decoder. Zero-filled IR(2:0) becomes Constant In Extended IR(8:6) || IR(2:0) and Bus A are address inputs to the PC. The PC is controlled by Branch Control logic The Control Unit Henry Hexmoor

  41. Branch Control determines the PC transfers based on five of its inputs defined as follows: N,Z – negative and zero status bits PL – load enable for the PC JB – Jump/Branch select: If JB = 1, Jump, else Branch BC – Branch Condition select: If BC = 1, branch for N = 1, else branch for Z = 1. The above is summarize by the following table: PC Function (continued) Henry Hexmoor

  42. The combinational instruction decoder converts the instruction into the signals necessary to control all parts of the computer during the single cycle execution The input is the 16-bit Instruction The outputs are control signals: Register file addresses DA, AA, and BA, Function Unit Select FS Multiplexer Select Controls MB and MD, Register file and Data Memory Write Controls RW and MW, and PC Controls PL, JB, and BC The register file outputs are simply pass-through signals: DA = DR, AA = SA, and BA = SBDetermination of the remaining signals is more complex. Instruction Decoder Henry Hexmoor

  43. The remaining control signals do not depend on the addresses, so must be a function of IR(13:9) Formulation requires examining relationships between the outputs and the opcodes… Observe that for other than branches and jumps, FS = IR(12:9) This implies that the other control signals should depend as much as possible on IR(15:13) (which actually were assigned with decoding in mind!) To make some sense of this, we divide instructions into types as shown in the table on the next page Instruction Decoder (continued) Henry Hexmoor

  44. T ruth T a ble for Instruction Decoder Logic Instruction Bits Contr ol W o r d Bits Instruction Function T ype 15 14 13 9 M B M D R W M W P L J B B C Function unit operations using 0 0 0 X 0 0 1 0 0 X X registers Memory read 0 0 1 X 0 1 1 0 0 X X Memory write 0 1 0 X 0 X 0 1 0 X X Function unit operations using 1 0 0 X 1 0 1 0 0 X X register and constant Conditional branch on zero (Z) 1 1 0 0 X X 0 0 1 0 0 Conditional branch on negative (N) 1 1 0 1 X X 0 0 1 0 1 Unconditional J ump 1 1 1 X X X 0 0 1 1 X Instruction Decoder (continued) Henry Hexmoor

  45. The types are based on the blocks controlled and the seven signals to be generated; types can be divided into two groups: Datapath and Memory Control (First 4 types) PC Control (Last 3 types) In Datapath and Memory Control blocks controlled are considered: Mux B (1st and 4th types) Memory and Mux D (2nd and 3rd types) By assigning codes with no or only one 1 for these, implementation of MB, MD, RW and MW are simplified. In Control Unit more of a bit setting approach was used: Bit 15 = Bit 14 = 1 were assigned to generate PL Bit 13 values were assigned to generate JB. Bit 9 was use as BC which contradicts FS = 0000 needed for branches. To force FS(6) to 0 for branches, Bit 9 into FS(6) is disabled by PL. Also, useful bit correlations between values in the two groups were exploited in assigning the codes. Instruction Decoder (continued) Henry Hexmoor

  46. The end result by use of the types, careful assignment of codes, and use of don't cares, yields very simple logic: This completes thedesign of most of the essential parts ofthe single-cycle simple computer Instruction Opcode DR SA SB 5 – 3 8 – 6 2 – 0 15 14 13 12 11 10 9 16 – 14 19 – 17 13 – 11 10 9 – 6 5 4 3 2 1 0 AA DA BA MB FS MD RW MW PL JB BC Control word Instruction Decoder (continued) Henry Hexmoor

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