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Standard Hardware API for MicroTCA.4 Systems

Standard Hardware API for MicroTCA.4 Systems. Bruno Fernandes Advance Electronics Group 5 th MicroTCA Workshop for Industry and Research DESY Hamburg. The Goal. Who are you? Which version? What can you do? What are you doing? What functions can you perform?.

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Standard Hardware API for MicroTCA.4 Systems

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  1. Standard Hardware API for MicroTCA.4 Systems Bruno Fernandes Advance Electronics Group 5thMicroTCA Workshop for Industry and ResearchDESY Hamburg

  2. The Goal Who are you? Which version? What can you do? What are you doing?What functions can you perform? A Standard Hardware API (SHAPI) architecture for use in xTCACommunity • structural and methodological approach to device access; • no restriction in communication channel or address mechanisms (how the software accesses it) • promote interoperability between hardware and software developed in different institutions; Courtesy: Struck Innovative Systems

  3. PICMG Committee

  4. Overview of Addressable I/O space Fundamental data access element is a register Registers are 32 bit wide • Standard set of registers that will • Identify the Hardware, Version and Vendor • Status and control of capabilities • Identify and control of device Interrupts • Addresses of all modules implemented • Identify the Module, Version and Vendor • Status and control of module’s capabilities • Possible to map all Modules in the Hardware

  5. Standard Device Register Set • Standard Device Register Set • Hardware/Device Vendor define by PICMG • Version has 3 fields that reflect software compatibility • Device Capabilities • Full, Soft Reset • RTM detection • Endianness • Device Status And Control bits mirror information in Device Capabilities • Scratch register • Available to the software to store internal information

  6. Standard Module Register Set • Standard Module Register Set • Information very similar to Standard Device register set • Module Vendor define by PICMG • Version has 3 fields that reflect software compatibility • Module Capabilities • Full, Soft Reset • RTM requirement • Multiple/Single Interrupts • Interrupts fields to support multiple interrupts sources and handling • Module-specific implementation registers follow the standard set

  7. Mapping of I/O Space ≠ 0 ≠ 0 • Address information allows for software to identify all implemented modules in device • First/Next Module Address has address of next Module Register Set initial register • Guideline covers devices with multiple BARs

  8. Interrupt Handling • SHAPI guideline also cover Device Interrupts • Up to 32 interrupts per device can be defined • Mask Interrupts • Definition for interrupt handling and priority • Modules can generate: • single interrupt but have multiple interrupt sources • multiple interrupts • Module Interrupt Identification • Compatible with devices that natively don’t support Interrupts

  9. SHAPI Standard Modules • Definition for modules which are commonly implemented across facilities • A Standard SHAPI module for DMA has already been defined • (Planned) Module for firmware update

  10. SHAPI Design Guide The SHAPI Design Guide version 1.0 was just committed for PICMG adoption • Includes Verilog SHAPI Reference implementation (Github repository)

  11. Thanks! Thank you for your attention! Questions/Suggestions? bruno.fernandes@xfel.eu

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