1 / 33

Why Assembly Language Programming?

Why Assembly Language Programming?. Unlocks the secrets of the hardware and software of a computer. Explains the way computer’s hardware and OS work together and how application programs communicate with OS. Provides more control over handling particular hardware. Advantages of ALP.

naif
Télécharger la présentation

Why Assembly Language Programming?

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Rachel Jiang, 2005 Why Assembly Language Programming? • Unlocks the secrets of the hardware and software of a computer. • Explains the way computer’s hardware and OS work together and how application programs communicate with OS. • Provides more control over handling particular hardware

  2. Rachel Jiang, 2005 Advantages of ALP • When programs run too slow, or are too large • assembly language might help getting your project under control • Who are interested in • learning how to write efficient code • Can easily bypass restrictions • imposed by high-level languages • Good assembly language programmers • make better High Level Language programmers • Understand the limitations of the compiler and know what it's doing with the code.

  3. Rachel Jiang, 2005 Application (Netscape) Operating Compiler System (Windows 98) Software Assembler Instruction Set Architecture Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors What are “Machine Structures”? • Coordination of many levels of abstraction Hardware

  4. Rachel Jiang, 2005 High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,MIPS) Assembler Machine Language Program (MIPS) Machine Interpretation Control Signal Specification Levels of Representation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $to, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 ° ° ° °

  5. Rachel Jiang, 2005 Address Bus • To differentiate memory locations and I/O devices • the system designer assigns a unique memory address to each memory element and I/O device. • When a software wants to access some particular memory location, it places the corresponding address on the address bus. • Circuitry associated with the memory recognizes this address and instructs the memory to • read the data from or • place data on the data bus.

  6. Rachel Jiang, 2005 Control bus • control how the processor communicates with the rest of the system. • Two lines on the control bus, read and write • which specify the direction of data flow. • read/write control lines control the direction of data on the data bus. • read line is low: the CPU is reading data from memory (system is transferring data from memory to the CPU). • write line is low: the system transfers data from the CPU to memory.

  7. Rachel Jiang, 2005 The ARC ISA

  8. Rachel Jiang, 2005 ARC Instruction and PSR Formats

  9. Rachel Jiang, 2005 Some useful terms • rd: target (destination) register • rs: source register (rs1, rs2) • imm22: constant 22-bit • Disp22:const. 22-bit to calc disp. For branch addr. • simm13: 13-bit immediate value • Sing extended to 32 bits • i field: immediate field • What is sign-extended?

  10. Rachel Jiang, 2005 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Sign-extended Example 1: X = 2064 in binary (13-bits): Result (in 32 bit):

  11. Rachel Jiang, 2005 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 1 1 0 0 Signed-extended Example2: Result (in 32 bit):

  12. Rachel Jiang, 2005 Register r1: Register r1: 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 0 1 1 1 0 0 1 1 1 0 0 2048 11111111 2049 Result: 11111111 1 1 1 1 1 0 2050 11111111 2051 11111110 ld instruction • Load a value from mem to r1: ld [x], %r1 !x=2048 Memory

  13. Rachel Jiang, 2005 I op op3 rs1 SIMM13 rd 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 Ld: Machine code • ex: ld [x], %r1 ! X = 2064(0,1000,0001,0000) 1 1 0 0 0 0 1 0 0

  14. Rachel Jiang, 2005 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 ld: Machine code • example: ld %r6, %r1 ! R6 = 2064 I op op3 rs1 rd rs2 1 1 0 0 0 0 1 0 0 0

  15. Rachel Jiang, 2005 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 11111111 00111111 00000111 11100111 1 1 1 1 1 0 11111111 11111111 11111110 11111110 st instruction • store a value in reg. to mem. (addr: 2064) Register r1: Result: original 2064 ex.: st %r1, [x] 2064

  16. Rachel Jiang, 2005 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 sethi • Set the MSBs 22 bits of a register with a const. contained with the instruction • This instruction also set the low 10 bits with 0s • Ex.: sethi 0x304f15, %r1 Register r1: original Result in r1 (After execute sethi instruction): 1 1 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 0 1 0 0 0

  17. Rachel Jiang, 2005 1 1 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 0 1 Machine code for sethi • Ex.: sethi 0x304f15, %r1 0 0 0 0 0 0 1 1 0 0

  18. Rachel Jiang, 2005 0 0 0 1 0 andcc • Bitwise and, set condition code. • Ex.: andcc %r1,%r2,%r3 • Machine code: rs2 i op rd op3 rs1 1 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0

  19. Rachel Jiang, 2005 Question: orcc • What is the machine code for orcc? • Ex.: orcc %r1,%r2,%r3

  20. Rachel Jiang, 2005 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 orcc • Ex.: orcc %r1, 1, %r1 • Set LSB of %r1 to 1 rd op op3 simm13 rs1 i 1 0 0 0 0 0 1 0 1 0

  21. Rachel Jiang, 2005 1 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 orncc • Bitwise NOR (set flags) • Ex. Orncc %r1, %r0, %r1 • Complement %r1 A B or nor 0 0 0 1 1 0 1 0 op rd rs1 i rs2 op3 0

  22. Rachel Jiang, 2005 Register r1: 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1 1 0 0 0 1 srl • Shift right logical operation • Ex: srl %r1, 3, %r2 Result in r2 (After execute the instruction):

  23. Rachel Jiang, 2005 Register r1: 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 Result in r2 (After execute the instruction): 1 1 1 1 1 0 1 1 0 0 0 1 sra • Shift right arithmetic operation • Ex: sra %r1, 3, %r2

  24. Rachel Jiang, 2005 Register r1: 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 sra • Ex: sra %r1, 3, %r2 Result in r2 (After execute the instruction):

  25. Rachel Jiang, 2005 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 Machine code for srl • Ex.: srl %r1, 3, %r2 • sra (not shown) simm13 rd op3 rs1 i op 1

  26. Rachel Jiang, 2005 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 addcc • add using binary 2’s complement, set flags • Ex.: addcc %r1, 5, %r1 rs1 op rd simm13 op3 1

  27. Rachel Jiang, 2005 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 call instruction • Call a subroutine and store addr. Of returning (current instruction) in %r15 • Effects a call and link operation • The addr. Of next instr. To be exe. Is calc. by adding 4xdisp30 (can be neg.) to addr of current instruct. • Ex.: call sub_r !25 words (100 bytes) farther disp30 op

  28. Rachel Jiang, 2005 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 jmpl • Return from subr. Jump to a new addr. • Store the addr. Of current instr (where jmpl is located) in dest. Register • Ex: jmpl %r15 + 4 op3 op rd simm13 r15 1

  29. Rachel Jiang, 2005 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 be • Branch if equal to zero • check zero flag (if set, branch) • Goto addr. 4xdisp22 + current addr. • If zero flag is not set, goto next instr. • Ex: be label !label is 5 words (20 byte further) Op2 (branch) op Cond (be) disp22

  30. Rachel Jiang, 2005 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 bneg • New addr. = 4xdisp22 + adrs. Of current instr. • Ex.: bneg label !jump to 5 words further in mem. • Disp22 can be negative disp22 cond op op2

  31. Rachel Jiang, 2005 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 bcs • Branch if codition code is set to 4xdisp 22 + addr. Of current instruction • Ex.: bcs label !jump to 5 words further in mem. disp22 cond op2 op

  32. Rachel Jiang, 2005 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 1 bvs • Branch if overflow flag is set • Jump to 4xdisp22 + addr. Of current instr. • Ex.: bvs label !jump to 5 words further in mem. disp22 cond op2

  33. Rachel Jiang, 2005 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 ba • Branch to 4xdisp 22 + addr. Of current instr. • Ex.: ba label !jump to 5 words further in mem. disp22 op2 Cond. op

More Related