NET+OS 6.1 Training

NET+OS 6.1 Training

PCI

NET+OS 6.1 PCI/Cardbus Driver • Supports • PCI Host • Cardbus • PCI Device • Assumptions • GNT/REQ pairs tied to DDI device • Arbiter always required in Host/never in Device • Type 0 PCI Headers only • See diagram #1

PCI Host API • Utilities to probe and configure devices on the bus • Maps external memory space to NS9750 memory space • Exposes NS9750 memory space • Utilities to trap Error conditions • Status Register Errors • Broken Masters • AHB Errors / System Errors (SERR) • Utilities to trap PCI Interrupts • INTA# through INTD#

Flow Diagram

Probing and configuring Devices • Uses DDI read() and write() • I/O Controls • PCI_GET_DEVICE_NUMBER • PCI_SET_DEVICE_NUMBER • PCI_SET_IO_BASE_ADDRESS • PCI_SET_MEMORY_BASE_ADDRESS

Exposing NS9750 memory space • I/O Controls • PCI_EXPOSE_LOCAL_MEMORY

Trapping Errors • I/O Controls • PCI_ARM_INTERRUPT • PCI_SET_INTERUPT_CALLBACK

Trapping Interrupts • I/O Controls • PCI_ARM_ERROR • PCI_SET_ERROR_CALLBACK

/PC1/0 /PC1/2 /PC1/1 INTA# ……… REQ1# REQ2# INTA# REQ# REQ# GNT1# RST# INTB# AD0-31 GNT2# RST# AD0-31 IDSEL GNT# RST# AD0-31 IDSEL GNT# NS9750 PCI Block diagram

Cardbus • Flow Diagram • Driver specs.

Flow Diagram

Open Cardbus Host State

Cardbus Driver • Works like a PCI Host. • Probe and configures Bus • Maps and Exposes memory spaces • Traps Errors and Interrupts • Cardbus services are also available. • Cardbus Socket Event Registers • CVS/CCD sensing pins • Cardbus Clock Stop mechanism

Cardbus Socket Event Registers • I/O Controls • PCI_GET_CARDBUS_SOCKET_EVENT_REGISTER • PCI_GET_CARDBUS_SOCKET_MASK_REGISTER • PCI_GET_CARDBUS_SOCKET_PRESENT_STATE_REGISTER • PCI_SET_CARDBUS_SOCKET_MASK_REGISTER • PCI_SET_CARDBUS_CALLBACK

CVS/CCD Sensing • I/O Controls • PCI_GET_CB_CCD1 • PCI_GET_CB_CCD2 • PCI_GET_CB_CVS1 • PCI_GET_CB_CVS2 • PCI_SET_CB_CVS1 • PCI_SET_CB_CVS2

Cardbus Clock stop mechanism • I/O Controls • PCI_STOP_CARDBUS_CLOCK

PCI Device • Utilizes early initialization. • BSP calls pciVeryEarlyInitialization() which calls the platform customizable function customizePCIStartup • Map external memory spaces to NS9750 Memory Space • Expose NS9750 Memory • Control the INTA# line

Device control over INTA# • I/O Controls • PCI_SET_PCI_INTERRUPT

PCI read int fd, result; pci_read_t readData; unsigned int configData[16]; fd = open ("/pci/2", O_RDWR); if (fd < 0) { return; } readData.function = pciFunc0; readData.headerType = pciType0; readData.busNumber = 0; readData.pDest = configData; readData.source = 0; result = read(fd, (char *)&readData, 16); if (result != 16) { return; }

PCI write int fd, result; pci_write_t writeData; unsigned int configData[16]; fd = open ("/pci/2", O_RDWR); if (fd < 0) { return; } configData[1] |= MC_PCI_COMMAND_REG_MEM_SPACE; writeData.pSource = &configData[1]; writeData.destination = 1; writeData.function = pciFunc0; writeData.headerType = pciType0; writeData.busNumber = 0; result = write(fd, (char *)&writeData, 1); if (result != 1) { return; }

PCI ioctl to expose local space pci_localMap_t AddressMap; pci_localMap_t *pAddrMap[2]; int locfd, result; locfd = open ("/pci/0", O_RDWR); if (locfd < 0) { return; } pAddrMap[0] = &AddressMap; pAddrMap[1] = NULL; pAddrMap[0]->bank = pciBank5; pAddrMap[0]->localAddress = (void *)0x900000; pAddrMap[0]->pciAddress = (void *)0xC0000000; result = ioctl(locfd, PCI_EXPOSE_LOCAL_MEMORY, (char *)pAddrMap);

PCI ioctl to map remote space pci_mMap_t devAddressMap; pci_mMap_t *pExtAddMap[2]; int fd, result; fd = open ("/pci/1", O_RDWR); if (fd < 0) { return; } pExtAddMap[0] = &devAddressMap; pExtAddMap[1] = NULL; pExtAddMap[0]->localAddress = pciAddr8000; pExtAddMap[0]->szOfBlock = pci64M; pExtAddMap[0]->pciAddress = APP_PCI_EXT_MEM_SPACE0; pExtAddMap[0]->bank = pciBank1; result = ioctl(fd, PCI_SET_MEMORY_BASE_ADDRESS, (char *)pExtAddMap);

NET+OS 6.1 Training