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Lecture 7 9/21/11

Lecture 7 9/21/11. Preliminary project ideas – brainstorming Today and Friday Everyone know how to use the logic analyzers? Flowcharts. Example Flowchart. main. Pulse. 1. PORTB=1. void Pulse (void) { PORTB=1; PORTB=0; } void main(void) { int count; while(1) { count=0;

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Lecture 7 9/21/11

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  1. Lecture 7 9/21/11 • Preliminary project ideas – brainstorming • Today and Friday • Everyone know how to use the logic analyzers? • Flowcharts

  2. Example Flowchart main Pulse 1 PORTB=1 void Pulse (void) { PORTB=1; PORTB=0; } void main(void) { int count; while(1) { count=0; do { count++; } while(count<10); Pulse(); } } count=0 PORTB=0 count=count+1 Return Y count<10 N Pulse 1 After Valvano, fig. 1.2

  3. Example Flowchart Entry Point main Pulse 1 PORTB=1 I/O Block void Pulse (void) { PORTB=1; PORTB=0; } void main(void) { int count; while(1) { count=0; do { count++; } while(count<10); Pulse(); } } count=0 Process Block PORTB=0 count=count+1 Return Y Decision count<10 N Pulse Function 1 Connector After Valvano, fig. 1.2

  4. A bad (unstructured) flowchart After Miller, fig. 4.4

  5. 3 allowed structures • SEQUENCE • IF-THEN-ELSE • DO-WHILE After Miller, figs. 4.5, 4.6, 4.9

  6. 2 “tolerated” structures • DO-UNTIL (loop body MUST execute once) • IN-CASE-OF (combination of IF-THEN-ELSE, i.e. switch or case statement) After Miller, figs. 4.12, 4.13

  7. Data Flow Graph Temperature Resistance Voltage Temperature Sensor Analog Amplifier ADC Timer Digital Sample Fixed-Point Temperature Fixed-Point Voltage LCD Display LCD Routines Temperature Calculation ADC Routines F or C Table Lookup Switch After Valvano, fig. 1.5

  8. Important 6811/12 instructions • Nice summary p.213ff of reference manual of instructions vs. addressing modes • Details near end of reference manual

  9. Some important instructions: LDAA LDA – load an 8-bit value into A or B : variants LDAA, LDAB; we note if U is between 0 and $FF direct addressing is used automatically (unless overridden); otherwise extended addressing is used. LDAA #w RegA = w LDAA U RegA = [U] LDAB #w LDAB U Set N,Z appropriately; V=0

  10. LDD LDD – load a 16-bit value into D, SP, X, or Y, variants LDD LDS LDX LDY LDD #W RegD = W LDD U RegD = {U} etc Sets N, Z appropriately; V=0 Note LDS #W is used to initialize the stack pointer in most programs, typically setting SP to the last word in RAM.

  11. MOVB/MOVW (6812 only) Memory-to-memory move 8(B) or 16(W) bits MOVB #w,addr [addr] = w MOVB addr1,addr2 [addr2] = [addr1] MOVW #W,addr {addr} = W MOVW addr1,addr2 {addr2} = {addr1} Why is immediate form still memory-to-memory? No flags

  12. STA/ST store 8/16 bit values in memory. Variants STAA STAB; STD STS STX STY STAA U [U] = RegA STD U {U} = RegD Sets N, Z appropriately; V=0.

  13. Inherent Register Instructions XGDX swap D,X XGDY swap D,Y CLC clear carry bit CLI clear interrupt but CLV clear overflow bit SEC set carry bit SEI set interrupt bit SEV set overflow bit TAP transfer A to CC (but cannot change X from 0 to 1) TPA transfer CC to A why use TAP/TPA for instance?

  14. Compares • Common error – numeric branch not immediately after compare/subtract CMP... Bxx... NOP NOP Bxx... Illegal even though Bxx and NOP don’t affect flags for numeric compares (BGE, BGT, BLE, BLT, BHI, BLO, BHS, BLS • BUT: Legal for non-numeric (flag-checking) compares • BCC, BCS, BEQ, BNE, BMI, BPL, BRA, BRN

  15. Compares - groupings • Numeric – must follow sub, cmp or test BGE Branch if signed .GE. BGT Branch if signed .GT. BLE Branch if signed .LE. BLT Branch if signed .LT. BHS Branch if unsigned .GE. (== BCC) BHI Branch if unsigned .GT. BLO Branch if unsigned .LT. (== BCS) BLS Branch if unsigned .LE.

  16. Compares - groupings • Logical – can follow any flag-setting instruction BCC/BCS C=0/1 BEQ/BNE Z=1/0 BMI/BPL N=1/0 BVC/BVS V=0/1 BRA Branch always BRN Branch never (!) JMP Branch always, extended addressing

  17. Useful summary table • From Freescale docs

  18. Compare/Subtract reprise CMPA #w RegA-w, set flags only CMPA U RegA-[U], set flags only SUBA #w RegA=RegA-w, set flags SUBA U RegA=RegA-[U], set flags TSTA RegA-0, set flags only

  19. Typical arithmetic compare 3 instruction sequence LDAA G2 (8 bit value) CMPA G1 (8 bit value) BNE next ; skip if not equal JSR isEqual ; G2 == G1 next ... Implements C code if(G2 == G1) { isEqual(); }

  20. BRN – the party line • from Freescale documentation Never branches. In effect, this instruction can be considered as a 2-byte NOP (no operation) requiring three cycles for execution. Its inclusion in the instruction set is to provide a complement for the BRA instruction. This instruction is useful during program debug to negate the effect of another branch instruction without disturbing the offset byte. Having a complement for BRA is also useful in compiler implementations.

  21. Increment/Decrement DECA DECB DEX DEY but no DED apparently..! DES – stack pointer – book left out INCA INCB INX INY INS – again book omitted Painful note: Most set Z; DECA and DECB set N,V but DEX DEY do not; DES sets no flags! (and similarly for INCs)

  22. Mul/Div MUL: 8bit8bit=16bit; inherent(!) RegD=RegA*RegB Cannot generate 16-bit overflow; up to programmer to check for 8-bit overflow if needed IDIV: 16bit by 16 bit unsigned divide with 16bit quotient, 16 bit remainder; also inherent! RegX=RegD/RegX with remainder in D FDIV: also 16 by 16 but pads D to 32 bits first RegX=(RegD*65536)/RegX with remainder in D

  23. Logical operations • Only 8-bit versions – i.e. no ANDD ANDA #w RegA = RegA&w ANDB U RegA = RegA&[U] COMA RegA=~RegA 1’s complement, inherent EORB #w exclusive or EORA U ORAA #w ORAB U BITA #w RegA&w – i.e. bitmask A with immediate, setting flags only! BITA U RegA&U – bitmask with byte from memory, set flags only • BITx instructions test a bitmask against A without changing A – logical version of a compare. • ALL logicals: set N, Z as appropriate and clear V; COM sets C

  24. Data Conversions char c; … c = getchar(); if isdigit(c) { val = c – ’0’; /* digit char val minus 0 char val is digit numeric val */ } else { /* error */ };

  25. Stack use Desktop Embedded CODE Constants Global + Heap Data RAM STACK

  26. Stack use Desktop Embedded CODE CODE Global + Heap Data Constants Global + Heap Data Constants RAM STACK STACK ROM/EEPROM RAM

  27. Bidirectional ports • Port C: bidirectional, but each pin one direction (input or output) at a time • DDRC “register” controls direction of each bit • DDRC actually memory location 0x1007 • CLR DDRC: all pins input • LDAA #$0F; STAA DDRC: pins 7-4 in 3-0 out

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