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This workshop held at NASA GSFC on October 12, 2005 discussed anomalies in EEPROM readings and writes for the Maxwell 79C0832 device used in the New Millennium Program. An anomaly was detected on Flight Unit #1 during ground testing in November 2003, showing different EEPROM checksums before and after a break. Further investigation revealed issues with write timings violating datasheet specifications. Recommendations included redesigning the FPGA to meet timing requirements and replacing the suspect EEPROM. Additional data retention screening was suggested by BAE Systems, highlighting the importance of proper testing and verification procedures for EEPROM reliability in aerospace applications.
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ST-5 EEPROM AnomalyKenneth LiCode 561NASA/GSFCKenneth.e.li@nasa.gov301-286-5777October 12, 2005 EEPROM Reliability Workshop - NASA GSFC, Oct 12, 2005
Background • Program: New Millenium Program, Space Technology – 5 (ST-5) • Device: Maxwell 79C0832 EEPROM (256Kx32) • MCM containing 8 1Mbit Hitachi 128Kx8 Die • Package: 96-Pin RAD-PAK Quad Flat pack • Implementation: Holds Boot and Flight Code for Mongoose 5 Processor EEPROM Reliability Workshop - NASA GSFC, Oct 12, 2005
Anomaly • Occurred on Flight Unit #1 during Ground Testing (Nov 2003) • Different EEPROM Checksums recorded before and after Thanksgiving break. EEPROM Reliability Workshop - NASA GSFC, Oct 12, 2005
EEPROM Reads Good Read – Expected 0s occur in ~60ns (Read BFC92244 - Data bits should show 0) CH1=D2 (on U58) CH2=D3 (on U58) CH3=D4 (on U58) CH4=EEP1_OE_N (JP42-12) – 600ns read cycle (used BNC cable instead of scope probe) Suspect Read – Expected 0s occur in up to 520ns Read BFC61628 - Data bits should show 0 CH1=D3 (on U58) CH2=D4 (on U58) CH3=EEP1_CE_N (JP42-8) CH4=EEP1_OE_N (JP42-12) EEPROM Reliability Workshop - NASA GSFC, Oct 12, 2005
EEPROM Writes All on U58 pins: CH1=D27 CH2=D28 CH3=CE0 CH4=WE_N Write a8650000 to BFC61944 All on U58 pins: CH1=D27 – writing a data 1 CH2=D28 – writing a data 1 CH3=CE0 CH4=WE_N TDH =10ns,min Write 7fc30000 to BFC61910 Result: Appears Write timing violates EEPROM Data Sheet Data Hold Spec EEPROM Reliability Workshop - NASA GSFC, Oct 12, 2005
Status • Appears EEPROM write timing violates datasheet spec • Signals generated by FPGA • FPGA redesigned to meet datasheet timing • However, suspect EEPROM replaced (Project decision) • No anomalies seen since • Suspect EEPROM installed onto ETU board • Testing of suspect EEPROM with new FPGA timing never performed by ST-5 (WOA still open) • Weak cells caused by inadequate write timing or by suspect EEPROM device (TBD) EEPROM Reliability Workshop - NASA GSFC, Oct 12, 2005
Miscellaneous – BAE Systems • BAE Systems has observed bit failures on EEPROMs in RAD750s • Suspect parts removed and sent back to Maxwell • Discovered at-speed timing not used in Maxell data retention tests • Consultation with Maxwell resulted in additional data retention screening, on request, comprising: • Program EEPROM to 0s with S/W write protect off & verify 0s with at speed timing • Burn-in for 72 hrs at 150C (unpowered) • Maxwell did not power off parts during their data retention tests. • Verify 0s at speed and deliver device programmed to 0s. EEPROM Reliability Workshop - NASA GSFC, Oct 12, 2005