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VHDL Coding Exercise 4: FIR Filter

VHDL Coding Exercise 4: FIR Filter. Where to start?. Feedback. Designspace Exploration. Algorithm. Architecture. Optimization. RTL- Block diagram. VHDL-Code. Algorithm. High-Level System Diagram Context of the design Inputs and Outputs Throughput/rates Algorithmic requirements

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VHDL Coding Exercise 4: FIR Filter

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  1. VHDL CodingExercise 4: FIR Filter

  2. Where to start? Feedback Designspace Exploration Algorithm Architecture Optimization RTL- Block diagram VHDL-Code

  3. Algorithm • High-Level System Diagram • Context of the design • Inputs and Outputs • Throughput/rates • Algorithmic requirements • Algorithm Description • Mathematical Description • Performance Criteria • Accuracy • Optimization constraints • Implementation constraints • Area • Speed FIR

  4. Architecture (1) • Isomorphic Architecture: • Straight forward implementation of the algorithm

  5. Architecture (2) • Pipelining/Retiming: • Improve timing • Insert register(s) at the inputs or outputs • Increases Latency

  6. Insert register(s) at the inputs or outputs • Increases Latency • Perform Retiming: • Move registers through the logic without changing functionality Backwards: Forward: Architecture (2) • Pipelining/Retiming: • Improve timing

  7. Insert register(s) at the inputs or outputs • Increases Latency • Perform Retiming: • Move registers through the logic without changing functionality Backwards: Forward: Architecture (2) • Pipelining/Retiming: • Improve timing

  8. Insert register(s) at the inputs or outputs • Increases Latency • Perform Retiming: • Move registers through the logic without changing functionality Backwards: Forward: Architecture (2) • Pipelining/Retiming: • Improve timing

  9. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain

  10. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain

  11. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  12. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  13. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  14. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  15. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  16. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  17. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  18. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  19. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  20. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  21. Architecture (3) • Retiming and simple transformation: • Optimization • Reverse the adder chain • Perform Retiming

  22. Architecture (4) • More pipelining: • Add one pipelining stage to the retimed circuit • The longest path is given by the multiplier • Unbalanced: The delay from input to the first pipeline stage is much longer than the delay from the first to the second stage

  23. Architecture (5) • More pipelining: • Add one pipelining stage to the retimed circuit • Move the pipeline registers into the multiplier: • Paths between pipeline stages are balanced • Improved timing • Tclock = (Tadd + Tmult)/2 + Treg

  24. Architecture (6) • Iterative Decomposition: • Reuse Hardware • Identify regularity and reusable hardware components • Add control • multiplexers • storage elements • Control • Increases Cycles/Sample

  25. RTL-Design • Choose an architecture under the following constraints: • It meets ALL timing specifications/constraints: • Throughput • Latency • It consumes the smallest possible area • It requires the least possible amount of power • Decide which additional functions are needed and how they can be implemented efficiently: • Storage of samples x(k) => MEMORY • Storage of coefficients bi=> LUT • Address generators for MEMORY and LUT=> COUNTERS • Control => FSM Iterative Decomposition

  26. RTL-Design • RTL Block-diagram: • Datapath • FSM: • Interface protocols datapath control:

  27. RTL-Design • How it works: • IDLE • Wait for new sample

  28. RTL-Design • How it works: • IDLE • Wait for new sample • Store to input register

  29. RTL-Design • How it works: • IDLE • Wait for new sample • Store to input register • NEW DATA: • Store new sample to memory

  30. RTL-Design • How it works: • IDLE • Wait for new sample • Store to input register • NEW DATA: • Store new sample to memory • RUN:

  31. RTL-Design • How it works: • IDLE • Wait for new sample • Store to input register • NEW DATA: • Store new sample to memory • RUN: • Store result to output register

  32. RTL-Design • How it works: • IDLE • Wait for new sample • Store to input register • NEW DATA: • Store new sample to memory • RUN: • Store result to output register • DATA OUT: • Output result

  33. RTL-Design • How it works: • IDLE • Wait for new sample • Store to input register • NEW DATA: • Store new sample to memory • RUN: • Store result to output register • DATA OUT: • Output result / Wait for ACK

  34. RTL-Design • How it works: • IDLE • Wait for new sample • Store to input register • NEW DATA: • Store new sample to memory • RUN: • Store result to output register • DATA OUT: • Output result / Wait for ACK • IDLE: …

  35. Translation into VHDL • Some basic VHDL building blocks: • Signal Assignments: • Outside a process: • Within a process (sequential execution): AxD YxD • This is NOT allowed !!! AxD YxD BxD • Sequential execution • The last assignment is kept when the process terminates AxD YxD BxD

  36. Default Assignment Translation into VHDL • Some basic VHDL building blocks: • Multiplexer: • Conditional Statements: AxD BxD YxD CxD SELxS AxD BxD SelAxS OUTxD CxD DxD SelBxS STATExDP

  37. Translation into VHDL • Common mistakes with conditional statements: • Example: AxD ?? • NO default assignment SelAxS OUTxD BxD • NO else statement ?? SelBxS STATExDP • ASSIGNING NOTHING TO A SIGNAL IS NOT A WAY TO KEEP ITS VALUE !!!!! => Use FlipFlops !!!

  38. Translation into VHDL • Some basic VHDL building blocks: • Register: • Register with ENABLE: DataREGxDN DataREGxDP DataREGxDN DataREGxDP DataREGxDP DataREGxDN

  39. Translation into VHDL • Common mistakes with sequential processes: DataREGxDN DataREGxDP CLKxCI • Can not be translated into hardware and is NOT allowed DataRegENxS DataREGxDN DataREGxDP 0 1 • Clocks are NEVER generated within any logic DataREGxDN DataREGxDP • Gated clocks are more complicated then this • Avoid them !!! CLKxCI DataRegENxS

  40. Translation into VHDL • Some basic rules: • Sequential processes (FlipFlops) • Only CLOCK and RESET in the sensitivity list • Logic signals are NEVER used as clock signals • Combinatorial processes • Multiple assignments to the same signal are ONLY possible within the same process => ONLY the last assignment is valid • Something must be assigned to each signal in any case OR There MUST be an ELSE for every IF statement • More rules that help to avoid problems and surprises: • Use separate signals for the PRESENT state and the NEXT state of every FlipFlop in your design. • Use variables ONLY to store intermediate results or even avoid them whenever possible in an RTL design.

  41. Translation into VHDL • Write the ENTITY definition of your design to specify: • Inputs, Outputs and Generics

  42. Translation into VHDL • Describe the functional units in your block diagram one after another in the architecture section:

  43. Translation into VHDL • Describe the functional units in your block diagram one after another in the architecture section:

  44. Translation into VHDL • Describe the functional units in your block diagram one after another in the architecture section: Register with ENABLE Register with ENABLE

  45. Translation into VHDL • Describe the functional units in your block diagram one after another in the architecture section: Register with CLEAR

  46. Translation into VHDL • Describe the functional units in your block diagram one after another in the architecture section: Counter Counter

  47. Translation into VHDL • Describe the functional units in your block diagram one after another in the architecture section:

  48. Translation into VHDL • The FSM is described with one sequential process and one combinatorial process

  49. Translation into VHDL • The FSM is described with one sequential process and one combinatorial process

  50. Translation into VHDL • The FSM is described with one sequential process and one combinatorial process

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