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KT 6144 / 6213

KT 6144 / 6213. Computer Systems Organization and Architecture. PROF. DR. KASMIRAN JUMARI DR. NASHARUDDIN ZAINAL. Course Synopsis.

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KT 6144 / 6213

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  1. KT 6144 / 6213 Computer Systems Organization and Architecture PROF. DR. KASMIRAN JUMARI DR. NASHARUDDIN ZAINAL

  2. Course Synopsis This course covers the following topics: Introduction to computer evolution, technology trends, system performance by Amdhal’s law. Computer structure that consists of structure & function of computer system, bus systems and bus arbitrations. Instruction Set Architecture (ISA) such as instruction set design issue and classifying ISA. Memory addressing such as addressing mode, CISC and RISC. ALU design. Computer architecture using MIPS architecture. Computer memory such as main memory design, memory hierarchy design, cache performance and virtual memory for paging and segmentation. Pipelining such as instruction pipeline, MIPS pipeline, pipelined vector processor and RISC pipelining. Parallel processors such as SIMD, MIMD, processors array, superscalar and I/O devices such as hard disk, RAID and multicore programming.

  3. Our Classes Attendance • Minimum 80%

  4. How you’ll be evaluated? We shall assign you :

  5. References Main Author: William Stallings Title: Computer Organization and Architecture Edition: 2010, 8th Edition Publisher: Pearson Others • Hennessy, J.L. & Patterson, P.A. 2007. Computer architecture: A quantitative approach, 4th Ed., Elsevier Science and Technology Book. • Hesham El-Rewini, Mostafa Abd-El-Barr.2005. Advanced computer architecture and parallel processing, Wiley. • Hill, M.D. 2009. Fault tolerant computer architecture, Morgan & Claypool Publishers. • Keckler, S.W., Olukotun K., Hofstee. H.P. 2009. Multicore processors and systems, Springer.

  6. Teaching Plan

  7. e-Learning • http://www.spin.ukm.my

  8. Course Outcomes • Ability to apply transfer register notation to describle data flow in CPUs • Ability to explain interrupt operation and exception handling mechanisms • Ability to compare main and virtual memory, and cache systems operation • Ability to design datapath logic in CPUs and microprogrammed control units

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