COEN 7501 Course Grading Scheme and Exam Details for VLSI Design and Verification
The grading scheme for COEN 7501 consists of an exam (40%) and a project (60%). The project evaluation includes a project report (20%), presentation (10%), peer evaluation (10%), and a demo evaluated by TAs (10%). Key project components involve RTL synthesis, equivalence checking, and verification processes. Important deadlines include project report submission by June 7, presentations on June 9, and the exam on June 16. Exam topics cover verification challenges, formal verification techniques, and model checking among others. Ensure all submissions meet originality requirements.
COEN 7501 Course Grading Scheme and Exam Details for VLSI Design and Verification
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COEN 7501 Grading Scheme • Exam: 40% • Project: 60%
COEN 7501 Grading Scheme • Exam: 40% • Project: 60%
COEN 7501: Project Grading Scheme • Project (60%) • 60% Project Report • 20% Project Presentation • 10% Participation (Peer Evaluation Form) • 10% Project Demo (TA’s Evaluation)
COEN 7501: Project Grading Scheme • Project (60%) • 60% Project Report • 20% Project Presentation • 10% Participation (Peer Evaluation Form) • 10% Project Demo (TA’s Evaluation)
COEN 7501: Project Report • max. 20 pages (w/o code) • Description of system behavior and function using state machines, block diagrams or circuit structures. • RTL synthesis using Synposys Design Compiler • RTL-gate level Equivalence Checking • Gate-gate level Equivalence Checking (bug hunting) • Description of Verification process in Synopsys Formality/Cadence Conformal • Analysis of verification results • Conclusions (Comments and Challenges)
COEN 7501: Project Grading Scheme • Project (40%) • 60% Project Report • 20% Project Presentation • 10% Participation (Peer Evaluation Form) • 10% Project Demo (TA’s Evaluation)
COEN 7501: Project Presentation • 20 min. Incl. Q&A (by TWO GROUPS!) • System behavior and function • RTL Synthesis • Equivalence Checking (RTL-gate/gate-gate) • Verification process • Analysis of results • Comparison Conformal vs. Formality • Conclusions (Comments and Challenges) • Presentation Skills • Answering Questions
COEN 7501: Project Grading Scheme • Project (40%) • 60% Project Report • 20% Project Presentation • 10% Participation (Peer Evaluation Form) • 10% Project Demo (TA’s Evaluation)
COEN 7501: Project Grading Scheme • Project (40%) • 60% Project Report • 20% Project Presentation • 10% Participation (Peer Evaluation Form) • 10% Project Demo (TA) • 0% Confirmation of Originality (mandatory!)
COEN 7501: Project Deadlines • Project Reports: • Monday June 7, before 5pm! • Mailbox of Dr. Tahar or ECE Dept. Secretary in EV005.139 • Project Presentations: • Wednesday June 9 at 6.30pm! • Classroom: H-401
COEN 7501: Exam • Wednesday June 16 at 6.30pm! • Classroom: H-401 • Extra Office Hours • Tuesday June 15 1-2.30pm • Topics …
COEN 7501: Exam Topics • Introduction • VLSI Design Flow • What’s verification • Verification Challenges • Types of Verification • Formal Verification (Techniques, Tools, Limitations, etc.) • Equivalence Checking • Combinational Equivalence Checking (Principles, Tools) • Propositional Resolution, Stalmark Procedure, ROBDDS • Sequential Equivalence Checking (Principles, Re. Anal.) • Case Study (ATM Switch) • Material allowed: Only Calculators (closed book!)
COEN 7501: Exam Topics • Model Checking • Temporal Logics (LTL, CTL) • Properties Specification • Model Checking Algorithm • Symbolic Model Checking • Case Study (ATM Switch) • Theorem Proving • First and Higher-order Logics • HOL Theorem Prover • Hardware Modeling in HOL • Hardware Verification in HOL • Case Study (RISC Processor) • Material allowed: Only Calculators (closed book!)
COEN 7501: Exam Topics • Introduction • VLSI Design Flow • What’s verification • Verification Challenges • Types of Verification • Formal Verification (Techniques, Tools, Limitations, etc.) • Equivalence Checking • Combinational Equivalence Checking (Principles, Tools) • Propositional Resolution, Stalmark Procedure, ROBDDS • Sequential Equivalence Checking (Principles, Re. Anal.) • Case Study (TSwitch) • Material allowed: Only Calculators (closed book!)
COEN 7501: Exam Topics • Introduction • VLSI Design Flow • What’s verification • Verification Challenges • Types of Verification • Formal Verification (Techniques, Tools, Limitations, etc.) • Equivalence Checking • Combinational Equivalence Checking (Principles, Tools) • Propositional Resolution, Stalmark Procedure, ROBDDS • Sequential Equivalence Checking (Principles, Re. Anal.) • Case Study (ATM Switch) • Material allowed: Only Calculators (closed book!)
COEN 7501: Exam Topics • Model Checking • Temporal Logics (LTL, CTL) • Properties Specification • Model Checking Algorithm • Symbolic Model Checking • Case Study (ATM Switch) • Theorem Proving • First and Higher-order Logics • HOL Theorem Prover • Hardware Modeling in HOL • Hardware Verification in HOL • Case Study (RISC Processor) • Material allowed: Only Calculators (closed book!)
COEN 7501: Exam Topics • Model Checking • Temporal Logics (LTL, CTL) • Properties Specification • Model Checking Algorithm • Symbolic Model Checking • Case Study (ATM Switch) • Theorem Proving • First and Higher-order Logics • HOL Theorem Prover • Hardware Modeling in HOL • Hardware Verification in HOL • Case Study (RISC Processor) • Material allowed: Only Calculators (closed book!)
COEN 7501: Last Remark Job Opportunities!
COEN 7501: Really Last Remark! • Teaching Evaluation Questionnaire: Don’t forget to do it <<on-line>> (Deadline Wednesday August 16!)
COEN 7501: Really Last Remark! • Teaching Evaluation Questionnaire: Don’t forget to do it on-line ASAP! … and now it’s time to go home! Thank you & Good Luck
