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Current Integrator (CI2005) Status

Current Integrator (CI2005) Status. Goal Specification Block diagram Status Issues Schedule. Feb.28.2006 Y.Fujita. Goal. Deadtimeless Current Integrator. Specification. Maximum Clock Freq.: ~ a few MHz Dynamic range : > 3V Resolution : ~ 0.02% INL : ~ 0.5% Amp spec

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Current Integrator (CI2005) Status

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  1. Current Integrator (CI2005) Status • Goal • Specification • Block diagram • Status • Issues • Schedule Feb.28.2006 Y.Fujita

  2. Goal • Deadtimeless Current Integrator

  3. Specification • Maximum Clock Freq.: ~ a few MHz • Dynamic range : > 3V • Resolution : ~ 0.02% • INL : ~ 0.5% • Amp spec • Differential input/output • GB product : ~100MHz • Gain >70dB • TDC a few nsec resolution for test • TMC type

  4. Block diagram Timing control CI CI CI SW Delay latch Integrator out TDC out

  5. TDC(TMC) part • TDC implemented for one of CI to confirm function • Timing resolution < 5nsec is easily achieved 0.5ns Residual 0ns - 0.5ns Output of Delay chain

  6. Status • Spec: Modified (TDC part added) • Simulation : Finished (CI only) • Layout : Ready (CI + TDC) • Submit : Jan 10th

  7. Layout (for 0.6um) Control circuit CI comp TMC

  8. Layout of single channel CI インバータ：遅延調整および波形整形 積分容量及びスイッチ 差動アンプ及びスイッチ

  9. Layout cont’d TDC TEG Delay Latch Buffer

  10. Issues for next production • Better INL • Droop (Drain - Source leakage?) • Test of CSMC version asap • TMC circuit modification • Filter implementation for TMC input signal • Easy operation (PLL etc) • Useful User I/F

  11. Schedule 2006 • New type CI : March 2006 • CMFB circuit modified • Test and modification • Specification finalize • Fab : June 2006 • Fab : Aug 2006

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