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Development and Performance Verification of the GANDALF High-Resolution Transient Recorder System

Development and Performance Verification of the GANDALF High-Resolution Transient Recorder System. COMPASS – Fixed Target Experiment. COMPASS – Experiment: 240 physicists from 11 countries and 28 institutions. COMPASS Facility (since 2002). Hadron Spectroscopy, Deep Inelastic Scattering.

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Development and Performance Verification of the GANDALF High-Resolution Transient Recorder System

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  1. Development and Performance Verificationof the GANDALF High-Resolution TransientRecorder System Sebastian Schopferer University of Freiburg IEEE RT 2010, Lisboa

  2. COMPASS – Fixed Target Experiment COMPASS – Experiment: 240 physicists from 11 countries and 28 institutions

  3. COMPASS Facility (since 2002) Hadron Spectroscopy, Deep Inelastic Scattering • polarized target (NH3 or LiD) • 2-stage spectrometer • several types of trackers • calorimeters (ECAL, HCAL) • PID (Muon-Filters, RICH) 50m μ 190 GeV/c high intensity (2∙107 s-1) large halo p,K

  4. COMPASS-II Upgrade COMPASS-II proposal: determination ofGeneralized Parton Distributions DVCS: mp  mpg μ Recoil Proton Detector: to ensure exclusivity of the observed process  COMPASS spectrometer: trackers, calorimeters, PID p μ 2,5m liquid hydrogen target

  5. Recoil Proton Detector (RPD) • measurement of: • time-of-flight (σ < 200ps) • energy deposit 0ns 40ns 0V μ  -4V high luminosity: separation of pile-up pulses is required p 4m inner barrel (A): Ø 0.50 m outer barrel (B): Ø 2.20 m

  6. 500Mhz Bandwidth Analog Inputs Digital Pulse Processing for real-time extraction of time, amplitude and integral information 12 bit 500MS/s ADCs 8 Analog Inputs VME64x Interface 16bit DACs for Offset Correction USB 2.0 VITA 41.0 VXS Interface TCS 8 Analog Inputs S-Link Interface to DAQ V5 SXT FPGAfor Data Processing V5 LXT FPGA for Memory Control & Data Output 144Mbit QDRII+ 4Gbit DDR2 Memories

  7. ADC Mezzanine Card • 8 ADC channels(12bit@500MS/s or 14bit@400MS/s) • optional time-interleaved mode • offsets are adjustable by DACs • gain is adjustable by changing some passive components • flexible input range (e.g. -4V..0V, -1V..0V, -2V..+2V, …)

  8. Advantage: High Resolution @ High Sampling Rate12bit @ 1Gsps Challenges Symmetric clock distribution Clock Jitter < 1ps Symmetric placement of devices Time Interleaved Mode 38.88MHz Exp. Clock DSPLL Clock System ADC FPGA AI Analog 500MHz 0° Analog IN 500MHz 180° ADC AI Time Digital Digital Time Time • Possible errors are corrected • Gain error • Offset error

  9. Sampling Clock Requirements ENOB = (SNR – 1.76) / 6.02

  10. Sampling Clock Quality TCS Jitter Sampling Jitter ADS5463 LMH6552 AnalogIN ADC 505.44MHz 155,52MHz TCS Receiver Clock Synth 900 fs ns ps Si5326 OCXO Jitter Sampling Jitter ADS5463 LMH6552 AnalogIN ADC 500MHz 20MHz OCXO Clock Synth 730 fs ns ps Si5326

  11. GANDALF Performance • Signal-to-Noise Ratio (Effective Number of Bits) Measurement Setup: AFG3252 and high performance band-pass filters LMH6552 ADC fin

  12. Fit Algorithms for Time Extraction • Digital Constant Fraction Discrimination Delay Fraction factor t meas.

  13. GANDALF dCFD Performance • create PMT-like pulses with function generator • pile-up pulses with amplitude and phase modulation timing resolution vs. pulse amplitude sampled in 1GS/s mode 40mV 4V

  14. GANDALF Laser Test PMT: RT1450 1.1 – 1.3kV Laser Pulser GAN DALF sampled in 1GS/s mode

  15. Fast Recoil Detector Trigger p outerLayer VITA 41.0 Specification GANDALF B VXS Backplane inner Layer Analog Inputs Bi-1 Ai-1 target A Ai Exp. Trigger μ Bi+1 i  Ai+1 Proton Trigger Trigger Processor geometric structure energy deposit vs. b t proton - t muon

  16. GANDALF as TDC & Logic Module Compact Flash Memory 64 channel LVDS/LVPECL inputs 1 NIM Input 2 NIM Outputs Implementation of TDCs, scalers, mean-timers, … inside the FPGA VME64x Interface to VME CPU NIM I/O (LEMO) 32 ch. LVDS input VME Interface, Board Config. To Backplane 32 ch. LVDS input NIM I/O (LEMO) NIM I/O (LEMO) 16 HS Channels via VXS to Switch HF CLK Data Processing, Analog Trigger Generation USB To Backplane Trigger & Clock TCS 64 channel LVDS/LVPECL inputs 1 NIM Input 2 NIM Outputs NIM I/O (LEMO) Memory Controller 32 ch. LVDS input To Transition 32 ch. LVDS input S-Link Interface via P2 NIM I/O (LEMO) NIM I/O (LEMO) QDRII 144Mb DDR2 4Gb

  17. GANDALF Mean-Timer OR cascade • 64 mean timer channels • max. time difference: 29 ns • resolution: 230 ps • variable input delay (max 8ns) to compensate cable lengths • mean-timer signals are fed into coincidence matrix • matrix pixels can be switched on/off on-the-fly (John Bieling, University of Bonn) „delay group“

  18. Generic Advanced Numerical Device for Analog and Logic Functions • … is a VME64x readout system for high energy physics • … is a transient recorder which meets all design goals: • Effective Number of Bits > 10 bit • Time resolution < 50 ps • … is a logic module with possibilities to implement TDC, Scaler, mean-timer and trigger matrix functionalities • … is a VXS payload board to allow multi-module trigger decisions

  19. Thanks for your attention!

  20. Backup

  21. Timing Resolution Methods converge at low amplitudes Constant Fraction reaches good timing resolution with very low calculation efforts! Spline algorithm reaches better timing resolution Timing Resolution

  22. Near following Pulses • Best achievable resolution fornear following pulses • Digital signal process developedfor double risetime range

  23. GANDALF Performance II Gain Adjustment 10bit ENOB Interleaved: 1GHz sampling rate Offset correction by DAC Gain correction by FPGA

  24. FPGA TDC Implementation • ShiftedClock Sampling

  25. Share FPGA Resources Constant Fraction

  26. Compact Flash Memory 8 Channel AD Conversion @ 500Msps 12bit 16bit offset DAC 8 Analog Inputs VME64x Interface VME Interface, Board Config. To Backplane low latency connection via VXS to Trigger Processor HF CLK Data Processing Online Feature Extraction USB To Backplane Trigger & Clock TCS 8 Channel AD Conversion @ 500Msps 12bit 16bit offset DAC Memory Controller 8 Analog Inputs To Transition Readout viaCERN S-Link Interface QDRII 144Mb DDR2 4Gb

  27. Digital Mezzanine Card NIM to TTL Buffer NIM I/O (LEMO) LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer 32 ch. LVDS input LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer High Density Connector Data Bus to GANDALF Board LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer 32 ch. LVDS input LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer LVDS Buffer TTL to NIM Buffer NIM I/O (LEMO) NIM I/O (LEMO)

  28. Messungen zur Zeitauflösung GANDALF Exp. Clock FAN OUT TIE 10ps / div Differenz der TIEs zwischen 2 GANDALF Boards: 5ps Zeit 2,5μs / div

  29. Transient Recorder Challenges • Defineandcalculatethetimeofthesignalshape • Time of Flight calculationwith a resolutionof< 200ps • Determinetheamplitudeofthesignalswithhighdynamicrange • Seperatesignalsfrompile-uppulses • Create a triggerforrecoilprotonsfrommultiple signalchannels

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