A Robust Pulse-triggered Flip-Flop and Enhanced Scan Cell Design

1. A Robust Pulse-triggered Flip-Flop and Enhanced Scan Cell Design Tarun Soni Rajesh Kumar Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station

2. Outline • Motivation • Scan Design • At Speed Scan Testing • Launch on Shift (LOS) • Launch on Capture (LOC) • Enhanced Scan Design • Pulse Flip Flops (PFFs) • Our Robust PFF • Our Pulse based Enhanced Scan Flip Flop (PESFF) • Experimental Results • Conclusion

3. Motivation • Decreasing process feature sizes increase the probability of defects during the manufacturing process • A single faulty transistor or wire can result in a faulty IC • Testing required to guarantee fault-free products • Design for testability (DFT) • Addresses testing issues during the design stage itself so that testing after implementation becomes easier • Scan design is the most popular DFT methodology used for sequential circuits

4. Scan Design D 0 Q D Q Q D D Q 1 SI SE CLK CLK • Replace all selected storage elements with scan cells • Connect scan cells into scan chains • Operated in three modes: • Normal mode • All test signals are turned off (i.e. SE is held low) • Shift mode • To shift data into and out of the scan cells (SE held high) • Capture mode • To capture test response into scan cells (SE is held low)

5. Scan design (continued) SCANIN = 111 Expected Output = 000 D Q0 0 1 Shift Shift Shift Capture Shift Shift Shift Q D SI SCANIN CLK SE CLK D SI SE Combinational Logic Q1 0 1 D Q SCANOUT Q0 SE CLK D SI Q1 Q2 0 1 D Q Q2 SE SCANOUT CLK

6. At Speed Scan Testing • Identifies transition delay fault by applying two vectors V1and V2 • V1 is used to initialize internal logic values of the circuit under test • V2 is used to launch transitions into the combinational circuit • Propagated output is captured in the scan chain by the system clock after launching V2 • Three ways to perform at speed scan testing • Launch on Shift • Launch on Capture • Enhanced Scan Design

7. Launch on Shift (LOS) V2 Launch Edge Capture Edge V1 CLK SE Launch cycle is last scan-in cycle Capture cycle Scan-out cycle Scan-in cycle Scan-in cycle • V2 is restricted to a one-bit shift of V1 • Requires fast scan enable signal

8. Launch on Capture (LOC) V2 Launch Edge Capture Edge V1 CLK SE Launch cycle Capture cycle Scan-out cycle Scan-in cycle Scan-in cycle • Uses two consecutive functional clocks to launch the transition and capture the output test response • Vector V2 is the response of the circuit under test to vector V1 • Lower fault coverage in comparison to LOS [Xu et. al. ‘07]

9. Enhanced Scan Design • Enhanced-scan cell stores two bits of data per input of the circuit under test • Achieved by adding a D latch to a muxed-D scan cell • No restriction on vector V2 • High fault coverage but with some area overhead D 0 Q D Q 1 D SCAN IN SI Q SE CLK

10. Our Contribution • Design of a robust PFF • Lower area and better timing than previous approaches • Modify this PFF for use in a pulse based enhanced scan flip-flop • Better timing than DFF based ESFF

11. Pulsed Flip-flops (PFF) Latch Data Clk Q D Pulse Pulse Generator Pulse Clk Clk Data Consists of a pulse generator and a latch The pulse is derived from system clock edge Hence data can arrive even after the clock edge (therefore Tsu may be negative)

12. Figure of Merit for a Flip-flop Combinational circuit D Q D Q CLK Time Period T ≥ Tcq+ Tsu + d where d – delay of the combinational circuit Tsu– setup time of the flip-flop Tcq–clock to Q delay of the flip-flop Since d is circuit-dependent, Tcq+ Tsuis the figure of merit for a flip-flop

13. Previous Work pulseb pulseb CLK D pulse CLKB CLK pulse Pulse generator Pulsed latch structure • Fast PFF (Venkatraman et al. 2008) • Pulse generation circuit is faster • Static power dissipation when CLK is high

14. Previous Work (continued) CLK pulse Q CLKB D • Explicit PFF (Zhao et al. 2002) • Uses dynamic pulse generator circuit and a static latch to achieve good setup time • Layout area is large and also power consumption is high

15. Previous Work (continued) D Q CLK CLK • Improved hybrid latch flip-flop (Goel et al. 2006) • Modified dynamic master stage of Explicit PFF to reduce power consumption • High clock to Q delay

16. Proposed PFF pulseb CLKB CLK pulseb pulse Q D Pulse generator pulse CLK Latch CLKB pulse

17. Pulse based Enhanced Scan Flip-flop (PESFF) PULSEB Q D 0 Q D D Q 1 D SCAN IN SI PULSEB PULSEB SEB SCANB SCAN PULSE SE CLK D SI Q Our robust PFF SCAN IN SE SCANB SCAN PULSE PULSE

18. PESFF (continued) SEB SEB SE SCAN SEB PULSE SCANB Capture Edge V2 Launch Edge V1 V1 V2 CLK PULSE SE SCAN

19. Experimental Setup • Implemented our PFF and PESFF in BPTM 100nm • Compared PFF with existing designs • Fast Robust Pulsed Flop (Venkatraman et al. 2008) • Explicit Flip-Flop (Zhao et al. 2002) • Improved hybrid pulsed Flip-Flop (Goel et al. 2006) • Traditional D Flip-Flop • Compared PESFF with traditional DFF based ESFF • Performed Monte Carlo simulations for all designs listed above • Varied supply voltage, channel length, threshold voltage • 3σ = 10% of the nominal value • 200 Monte Carlo simulations

20. Experimental Results - PFF

21. Experimental Results - PESFF Pulse generator has been shared among 10 latches to reduce area and power overhead

22. PESFF PULSEB PULSEB SEB SCANB SCAN D SI Q SCAN IN SE SCANB SCAN PULSE PULSE

23. Conclusion • The performance of our PFF design is better than existing PFF designs • 18% better Tcq+ Tsuthan explicit PFF • 14% lower power dissipation than Fast PFF • 60% lower standard deviation of Tcq+ Tsucompared to Fast PFF • 16% lower area in compared to Fast PFF • No earlier PFF based enhanced scan design • 14% better Tcq+ Tsuthan traditional DFF based ESFF • 105% area overhead compared to traditional DFF based ESFF • Selective replacement gives considerable coverage improvement with small area overhead

24. Thank You