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S01: Introduction to HDLWorld

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S01: Introduction to HDLWorld

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  1. Introduction to Digital Hardware Design S01: Introduction to HDLWorld Dr. Khaled Benkrid (Author) k.benkrid@ieee.org Reviewed and updated by; Prof. W. Adi

  2. Course Specification • Aim • To produce students who are capable of developing synchronous digital circuits from high level functional specifications and prototyping them on to FPGA hardware using a standard hardware description language (Verilog in our case) • Pre-requisites: • Knowledge and understanding of the basics of combinational and synchronous digital circuits

  3. Course Specification • Objectives • To explain and illustrate combinatorial and sequential circuits and present a number of ways of designing, and capturing them in a standard hardware description language; • To explain and illustrate basic and linked state machines for controlling circuit behaviour, and present a number of ways of designing, and capturing them in standard hardware description language; • To explain and illustrate the notion of “modular design” and “design for reuse”, and ways of capturing this in a standard hardware description language; • To present a digital circuit development flow that captures functional specification, design, simulation, synthesis, implementation and testing on FPGA hardware, and illustrate it using a commercial tool suite.

  4. Course Timetable – 1/4 • Section 1 • 30 Min: Introductory lecture • 3 hours: Lab session 1: "HelloWorld" and "HelloLotsofWorlds" modules, with 15mn break in between • 30 Min: Lecture on sequential digital hardware • 3 hours: Lab session 2: “HelloSynchronousWorld", "ShiftingTheWorld" and "ShiftingManyWorlds" lab modules, with 15mn break in between

  5. Course Timetable 2/4 • Section 2 • 30 min: Lecture on combinational digital hardware • 3 hours: Lab session 3: "CountingTheWorld" and "TimingTheWorld" modules, with 15mn break in between • 30 min: Short lecture on coding styles • 3 hours: Lab session 4: "DecodingTheWorld" module, with 15mn break in between

  6. Course Timetable 3/4 • Section 3 • 30 min: Short lecture on the BASYS 2 board’s 7-Segment Displays • 3 hours: Lab session 5: "TimingTheWorldInDecimalNow" module, with 15mn break in between • 30 min: Short lecture on the BASYS 2 board’s VGA port • 3 hours: Lab session 6: "ColouringTheWorld" module, with 15mn break in between

  7. Course Timetable 4/4 • Section 4 • 30 min: Introduction to state machines • 3 hours: Lab session 7: "TheWorldofStateMachines" and "TheWorldofLinkedStateMachine" modules, with 15mn break in between • 30 min: Short lecture on the Snake Game • 3 hours: Lab session 8: "SNAKE" Game module, with 15mn break in between

  8. An Introduction to FPGAs Reconfigurable Input/Output Cell Reconfigurable Logic Cell Programmable Switch Block Specific blocks (e.g. Memory, Multipliers, Embedded Processors ) Programmable Routing switches • Generic Field Programmable Gate Arrays (FPGAs) architecture

  9. An Introduction to FPGAs Programmable Switch Block Programmable routing Switch X X X X X X X X X X Programmable Switch • Generic Field Programmable Gate Arrays (FPGAs) architecture • Most commercial FPGAs are based on SRAM technology (volatile). Others include non-volatile Flash and one-time programmable fuse technology.

  10. An Introduction to FPGAs • Xilinx’ Virtex-5 FXT FPGA Input/Output e.g. 6.5 Gbps serial links, up to 1200 pins Configurable Logic Blocks (CLBs) 50,000+ (Up to 500MHz) PowerPC 440 @550MHz DSP48 Blocks (e.g. MACs) BlockRAMs 288x36Kb PCI-e Interface

  11. An Introduction to FPGAs • Xilinx’ Virtex-5 FXT FPGA: CLB architecture

  12. Computing Platform Alternatives 1/2 • General Purpose Processors (GPPs) e.g. Pentium • Software reprogrammableand general purpose • Field Programmable Gate Arrays (FPGAs) • Field CustomisableReprogrammable hardware • Application-specific processor (ASIPs), e.g. DSP • Software reprogrammable, optimised for a particular class of applications • Fixed Application Specific Integrated Circuits (ASICs) • Non reprogrammable, fully customised to only the application in hand

  13. Computing Platform Alternatives 2/2 Flexibility Speed Performance

  14. Why FPGAs? Memory Arithmetic Logic Unit e.g. MAC Control Unit • Unlike ASIPs/GPPs, FPGAs are not constrained by the Von Neumann architecture • FPGAs have ASIC-like performance and power consumption, with the additional re-programmability feature • FPGAs have a shorter development cycle, lower Non-Recurring Engineering costs compared to ASICs • FPGAs are nowadays widely used in Telecommunications, networking, automotive, industrial and consumer electronics • They are also widely used for prototyping ASIC designs before fabrication Instructions executed sequentially cycle by cycle in a Von Neumann architecture

  15. FPGA Programming Tools • FPGA are programmed through a bit-file which describes the configuration of all switches in the fabric • FPGA Programming tools have improved greatly since FPGAs’ early days in the mid 1980’s: • Schematic design: mid-80’s – 90’s • Hardware Description Languages (HDLs): 90’s - Present • Structured (Geometric) hardware design environments: 90’s - present • Graphical design environments: 90’s - present • Object-Oriented hardware design languages: 90’s - present • Hardware design languages from High Level Languages (HLLs): 90’s – present

  16. FPGA Programming Tools Design entry Schematic capture Library of symbols FDC Data Dout CLK EN Schematic to Netlist converter Gate level netlist e.g. EDIF, XNF, … Place-and-route FPGA Configuration 1 - Schematic Design • Since the early days of the technology • Intuitive way of designing circuits • Technology dependent • Not programmatic though – Not easy to scale up and parameterise • Not easy to port to other tools/environments

  17. FPGA Programming Tools Hardware Description Languages (HDLs) e.g. Verilog module Multiplexor_2_to_1( input In0, input In1, input Select, output reg Out ); always@(In0 or In1 or Select) ….. endmodule Design entry HDL Synthesis Gate level netlist e.g. EDIF, XNF, … Place-and-route FPGA Configuration 2- Hardware Description Languages (HDLs) • Became more popular since mid-1990’s • Programmatic approach – easy to scale up and parameterise • Easy to port to other tools/environments • Industry standard HDLs: VHDL, Verilog • Can describe circuits at different levels of abstractions

  18. FPGA Programming Tools Select[1] Select[0] In0 0 Out In1 1 Multiplexer_4_to_1 2 In2 3 In3 2- Hardware Description Languages (HDLs) • Behavioural Description • Describes how the circuit behaves • Borrows high level language constructs (procedure calls, control structures etc.) • Can include time delays • Saves design time at the expense of some loss of implementation efficiency module Multiplexor_4_to_1( input In0, input In1, input In2, input In3, input [1:0] Select, output reg Out ); always@(In0 or In1 or In2 or In3 or Select) case (Select) 2’b00 : Out = In0; 2’b01 : Out = In1; 2’b10 : Out = In2; 2’b11 : Out = In3; endcase endmodule

  19. FPGA Programming Tools In0 In2 In1 In3 0 1 0 1 Select[1] Mux_1 Mux_2 Multiplexer_2_to_1 Multiplexer_2_to_1 0 1 Select[0] Mux_3 Multiplexer_2_to_1 Out 2- Hardware Description Languages (HDLs) • Structural Description • Component-based design • Could be used as the text equivalent of schematic entry • Can result in highly efficient implementations module Multiplexer_4_to_1( input In0, input In1, input In2, input In3, input [1:0] Select, output reg Out ); wire temp1, temp2; Multiplexer_2_to_1 mux_1( .In0(In0), .In1(In2), .Select(Select[1]), .Out(temp1) ); Multiplexer_2_to_1 mux_2( .In0(In1), .In1(In3), .Select(Select[1]), .Out(temp2) ); Multiplexer_2_to_1 mux_3( .In0(temp1), .In1(temp2), .Select(Select[0]), .Out(Out) ); endmodule1

  20. FPGA Programming Tools • Most hardware designs include a mixture of the above abstraction levels • We also distinguish between synthesisable HDL code and non-synthesisable HDL code • Synthesisable HDL is HDL code that can be compiled and mapped on to hardware • Non-synthesisable HDL is HDL code which cannot be compiled and mapped into hardware. It is often used for simulation purposes • Most HDL languages (e.g. Verilog, VHDL) have a synthesisable subset and a non- synthesisable one

  21. FPGA Programming Tools module D_Flip_Flop_testbench; // Inputs reg CLK, IN; // Outputs wire OUT, OUTBAR; // Instantiate the Unit Under Test (UUT) HelloSynchronousWorld uut ( .CLK(CLK), IN(IN), .OUT(OUT), .OUTBAR(OUTBAR) ); initial begin CLK = 0; forever #100 CLK = ~CLK; end initial begin // Initialize Inputs IN = 0; #50 IN = 1; #50 IN = 0; #200 IN = 1; #20 IN = ~IN; #100; end endmodule module D_Flip_Flop( input CLK, input IN, output reg OUT, output reg OUTBAR ); always@(posedge CLK) begin OUT <= IN; OUTBAR <= ~IN; end endmodule Synthesisable Verilog Code Non-synthesisable Verilog Code (Testbench for simulation)

  22. Software/Hardware Used in The Lab • In this course, you will learn to use a standard Hardware Description Language called Verilog for FPGA hardware programming • You will target real FPGA hardware in the form of a BASYS2 FPGA card from DIGILENT, Inc, which has a Spartan 3E FPGA chip from Xilinx, Inc. • You can purchase the board from Digilent Inc. for ~US $50 (http://www.digilentinc.com/)

  23. Software/Hardware Used in The Lab The FPGA hardware development software suite that you will use in the labs is Xilinx ISE You can download a free version of ISE called WebPACK from Xilinx website: http://www.xilinx.com/support/download/index.htm With the free WebPack software and the BASYS2 board, you can develop your digital hardware skills from home or from anywhere else!

  24. Software/Hardware Used in The Lab

  25. Lab Session 1 The first lab session (HelloWorld and HelloLotsofWorlds modules) will introduce & familiarise you with the tools used throughout this lab (Xilinx ISE) and Digilent BASYS2 board. You will also implement your first piece of HDL code on reconfigurable hardware