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A Practical Guide to DDR2 Design with Spartan-3A DSP

A Practical Guide to DDR2 Design with Spartan-3A DSP. Featuring ISE 9.2 and the Xilinx Spartan-3A DSP 1800A Starter Platform. Course Objectives. By the end of the day, you will Build a functioning DDR2 controller in hardware Know what’s required to design your own board. Morning Agenda.

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A Practical Guide to DDR2 Design with Spartan-3A DSP

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  1. A Practical Guide to DDR2 Design with Spartan-3A DSP Featuring ISE 9.2 and the Xilinx Spartan-3A DSP 1800A Starter Platform

  2. Course Objectives By the end of the day, you will • Build a functioning DDR2 controller in hardware • Know what’s required to design your own board

  3. Morning Agenda • Memory, FPGAs, and Memory Controllers • Memory trends • DDR2 signaling • Xilinx FPGA memory controllers • Memory Interface Generator (MIG) • Lab 1 – Generate a DDR2 controller core • Real-world Design with a MIG DDR2 Controller • Interface to the MIG controller • Logically simulate • Hardware debug • Lunch Break

  4. Afternoon Agenda • Lab 2 – Build and verify a DDR2 controller in hardware • PCB Considerations • FPGA pinout • Factors impacting signal quality and crosstalk • PCB simulation example for DDR2 • Trace requirements • Power • Customizing and Verifying the MIG Results • Pinout rules • Pin-swapping • Verifying a new design • Lab 3 – Analyze and Fix Customized MIG Controllers

  5. A Practical Guide to DDR2 Design with Spartan-3A DSP Memory, FPGAs, and Memory Controllers

  6. Memory, FPGAs, and Memory Controllers • Memory, FPGAs, and Memory Controllers • Memory trends • DDR2 signaling • Xilinx FPGA memory controllers • Memory Interface Generator (MIG) • Lab 1 – Generate a DDR2 controller core • Real-world Design with a MIG DDR2 Controller • Interface to the MIG controller • Logically simulate • Hardware debug • Lunch Break

  7. The FPGA/Memory Interface • Memory interface success in an FPGA is dependent on many things • FPGA fabric • Controller • Memory • Clock • PCB Layout • Power • We’ll cover all these topics today Termination Termination Memory Controller FPGA Power Clock PCB

  8. DDR2 Interface Covered Today • FPGA • Spartan-3A DSP XC3SD1800A • Memory • Micron DDR2 MT47H32M16 • Controller • Xilinx Memory Interface Generator (MIG) • PCB/Power/ Terminations • Avnet-designed Spartan-3A DSP 1800A Starter Platform

  9. Why DDR2? • Compared to DDR-1 • Less expensive • More readily available • Lower power • Larger varieties • On-die termination (ODT) • We’ll show details on this later • Differential strobes • Compared to DDR-3 • More mature • Easier to get • Better controller support

  10. DRAM Market and Technology Trend DRAM Shipments by Memory Technology Type • DDR2 is the prevalent architecture 2007-2009 • DDR is still widely used (low end applications) • DDR3 is the upcoming technology 8000 7000 DDR3 6000 DDR2 5000 DDR Units (Millions) 4000 SDRAM RDRAM 3000 EDO 2000 FP / EDO 1000 0 2002 2003 2004 2005 2006 2007 2008 2009 Slide Courtesy Xilinx Forecast Year Note: The DDR3 forecast seems very optimistic Data Source: iSupply

  11. DDR SDRAM Component Comparison *Raw speed of memory device, NOT necessarily the speed the FPGA controller can run

  12. Memory Organization Column • Organized as • Banks • Rows • Columns • Each needs addressing Bank 0 Row Bank 1 Bank 2 Bank 3 DDR2

  13. Bank Management 4 or 8 banks per memory device • Latency to open a row • Latency to close a row Other devices can have different rows open Any 1 row per bank can be open Slide courtesy Xilinx

  14. Bank Interleave • Left side has bank/row conflicts – same row in bank -> conflict! • Right side shows banks changing, but no conflict • Higher throughput with bank interleave Conflicts (gaps for activate, precharge) No Conflicts (no gaps) Slide courtesy Xilinx

  15. Row/Column Addressing • Interface on S3ADSPSK is 32Mx32 (128 MB or 1 Gbit) • Two chips (each 32Mx16) • Each chip consists of 4 banks • Each bank has 8K rows and 1K columns • Each memory location stores 16 bits • 2 chips * 4 banks * 8K rows * 1K columns * 16 bits = 1Gbit • Linear addressing requires 25 address bits • Our interface has 15 total address bits • 13 ADDRESS (A) and 2 BANK ADDRESS (BA) • BA[1:0] selects one of four banks • A[12:0] with RAS selects one of 8K rows in the bank • A[9:0] with CAS selects one of 1K columns in the row

  16. Control Signals • Combination of RAS, CAS, and WE determine action • RAS asserted = Open Row • Bank Address and Row Address latched in • CAS and WE asserted = Write • Column address latched in • Write enabled • CAS asserted = Read • Column address latched in • RAS and WE asserted = Close Row (PRECHARGE) • Row deactivated • ‘1’ means asserted (which is active low)

  17. ..... Read Example • RAS asserted opens row • Latches bank and row addresses • Bank 3 • Row 0x000C • CAS asserted by itself identifies the operation as read • Latches the column address • Column 0x0000 • With row open, multiple reads can be performed by re-asserted CAS • Column 0x0008

  18. Multiple Reads • Five subsequent reads from the same row shown • Burst length for this example is 8 • Each time CAS asserts, 8 words are read • 40 total words are read in this diagram • Close row (Pre-charge) shown after reading • RAS and WE simultaneously asserted

  19. ..... Write Example • RAS asserted opens row • Latches bank and row addresses • Bank 3 • Row 0x000C • CAS and WE asserted together identifies the operation as write • Latches the column address • Column 0x0000 • With row open, multiple writes can be performed by re-asserted CAS and WE • Column 0x0008

  20. Multiple Writes • Five subsequent writes from the same row shown • Burst length for this example is 8 • Each time CAS/WE assert, 8 words are written • 40 total words are written in this diagram • Close row (Pre-charge) shown after reading • RAS and WE simultaneously asserted

  21. Data Interface • One strobe (DQS) per 8 bits of data (DQ) • DQS is a local clock for each data byte • Can be differential • One mask (DM) per 8 bits of data (DQ) • Selects which bytes are active during a write (byte enable) • 32-bit interface has 32 DQ, 4 DQS, and 4 DM bits • FPGA outputs DQS center aligned to the data for a write • FPGA receives DQS edge aligned from the memory on a read DQS DQS DQ DQ DATA WRITE FPGA  DDR2 DATA WRITE DDR2  FPGA

  22. Clock • Differential – CK and CK# • One clock pair per DDR2 chip • Since S3ADSPSK has 2 DDR2 chips, the FPGA outputs 2 clock pairs • Address and control signals are registered at every positive edge of CK • DQ and DQS outputs from DDR2 aligned with clock • DDR2 uses an internal Delay Locked Loop (DLL) • DLL has both a minimum and maximum frequency • DDR2 specifications based on operating within this frequency range (125 MHz to 533 MHz)

  23. On-Die Termination • ODT = On-Die Termination • Enables built in stub termination on DDR2’s data interface • Eliminates need for stub termination resistors on the DDR2 side for data • Adjustable: 50Ω, 75Ω, or 150Ω

  24. FPGA Interface ADDRESS BANK ADDRESS RAS CAS WE DQ DDR2SDRAM FPGA DQS DM CLK CLK_EN CS ODT RST_DQS_DIV

  25. Why Do I Need a Controller? • Easier to interface to a controller than directly to the memory • Manages multiple operations • Initialization • See the DDR2 datasheet excerpt • Calibration • Shift outgoing DQS by 90 degrees • Shift incoming DQS by 90 degrees • Refresh DRAMs • Simplified interface • 4 potential commands instead of 15 • Initialize command to MIG controller spawns 13 commands to DDR2 Reduces the design effort

  26. Memory Interface Generator (MIG) • Free utility to create a custom FPGA/memory interface • Based on real, working, tested hardware • Documented in Xilinx Application Notes (XAPP) • Customized outputs include • RTL source for the memory controller in Verilog or VHDL • Simulation testbench and support • User Constraint File (UCF) • Pinout specific for chosen FPGA device/package • Logic block locations • FPGA timing constraints • Batch files for processing • Run ISE tools in command line mode • Convert to ISE Project Navigator Project • Timing analysis • Documentation

  27. MIG v2.0 Component Controllers Fastest clock rate in fastest FPGA speed grade See http://www.xilinx.com/support/answers/29446.htm

  28. MIG v2.0 DIMM Controllers Fastest clock rate in fastest FPGA speed grade See http://www.xilinx.com/support/answers/29446.htm

  29. Spartan-3/3A DDR2 Controller • Performance • Up to 166 MHz / 333 Mbps in -5 Speed grade device • 200 MHz specific implementation documented in XAPP458 • 133 MHz/266 Mbps in -4 Speed grade device • Spartan-3A only supports left and right sides • Data Width • Based on total available pins • Component • Up to 72-bit in Spartan-3 • Up to 64-bit in Spartan-3A/3AN/3ADSP • DIMM • 64- and 72-bit in Spartan-3 • 64-bit in Spartan-3A/3AN/3ADSP • DQ to DQS Ratio is 8:1 • No built-in bank management for Spartan controllers • Virtex-5 has 4-bank Least Recently Used option

  30. Embedded Processor Controllers • Interface DDR2 to a MicroBlaze processor • Embedded Development Kit (EDK) 9.2 • Includes the Multi-Port Memory Controller v3 (MPMC3) • MIG used for the physical layer • All MIG rules and constraints apply • See Answer Record 29221 • http://www.xilinx.com/support/answers/29221.htm • Still set XIL_ROUTE_ENABLE_DATA_CAPTURE • Use script to include MIG UCF in MicroBlaze system UCF • Verify design built correctly (see Lab 3)

  31. Where do I get MIG? • MIG is included with ISE Foundation/WebPACK • Part of CORE Generator • Graphical User Interface (GUI) provides access to • Core library • Datasheets • 3rd party contact information • Available Xilinx Solution Records • Must Install ISE IP update • MIG v2.0 in ISE 9.2 IP Update 2 • Get IP Updates at www.xilinx.com/download • Find more information at www.xilinx.com/memory • WebPACK • WebPACK is free! • WebPACK supports XC3SD1800A on S3ADSPSK • www.xilinx.com/webpack

  32. MIG Documentation • MIG User’s Guide (UG086) • Xilinx Application Notes • XAPP768c (Spartan DDR) • XAPP454 (Spartan DDR2) • XAPP458 (Spartan-3A Starter 200 MHz DDR2) • XAPP858 (Virtex-5 DDR2) • XAPP701 & XAPP702 (Virtex-4 DDR2 Direct Clocking) • XAPP721 & XAPP723 (Virtex-4 DDR2 SERDES) • Virtex-5 ML561 Memory Interfaces User’s Guide (UG199)

  33. ... MIG Design Flow With Project Navigator Project Navigator Integrate Design Core Generator MIG Download Design to Hardware create_ise.bat MIG Outputs

  34. A Practical Guide to DDR2 Design with Spartan-3A DSP Lab 1 – Generate a DDR2 Controller with MIG

  35. Lab 1 Overview • Run COREGen • Run MIG • Configure controller • Generate • Convert to Project Navigator • Review raw outputs • HDL • UCF • Build scripts Project Navigator Integrate Design Core Generator MIG Download Design to Hardware MIG Outputs

  36. Lab 1 Review • What are the benefits of using MIG? • What is required to use Project Navigator with a MIG design? • Other observations? • Pinouts match our board? • What else did you notice about the UCF? • Properties match between ProjNav and command-line script?

  37. A Practical Guide to DDR2 Design with Spartan-3A DSP Real-world Design with a MIG DDR2 Controller

  38. Real-world Design with a MIG DDR2 Controller • Memory, FPGAs, and Memory Controllers • Memory trends • DDR2 signaling • Xilinx FPGA memory controllers • Memory Interface Generator (MIG) • Lab 1 – Generate a DDR2 controller core • Real-world Design with a MIG DDR2 Controller • Interface to the MIG controller • Logically simulate • Hardware debug • Lunch Break

  39. . MIG Output Block Diagram Memory MIG Outputs User Logic Memory Controller Clock Clock Management Calibration FPGA

  40. User Logic Operating Modes • Initialize • User instructs controller to set up the DDR2 for operation • Controller programs DDR2 with operating parameters • Parameters established by user during MIG generation • Write • User instructs controller to write data to memory • Controller writes the data to the DDR2 • Read • User instructs controller to read data from memory • Controller reads the data from the DDR2 • Refresh • Controller tells user a refresh is needed • User pauses while controller handles refresh

  41. Clock Domains in the User Logic • 90-degree phase of DDR2 clock • Used for all data-related signals • Generated by a DCM • Referred to as CLK90 • 180-degree phase of DDR2 clock • Used for all control-related signals • Generated by negative edge of 0-phase clock • Referred to as CLK180 or Falling Edge CLK0 • Why is this important? • User logic controls interaction between domains • User must manage multiple clocks and resets

  42. User Interface Signals Write Data Write Mask Address Burst Done Command Command Acknowledge Controller User Logic Read Data Data Valid Initialization Complete Auto Refresh Request Auto Refresh Done Clocks & Resets Clocks & Resets

  43. Initialize Command Controller User Logic Initialization Complete Clocks & Resets Clocks & Resets

  44. How to Initialize • Wait for RST_90 and RST_180 to deassert • Set USER_CMD to b’010 on CLK180 for one clock • Wait for INIT_DONE to assert • Minimum of 200 s

  45. Write Write Data Write Mask Address Burst Done Command Command Acknowledge Controller User Logic Clocks & Resets Clocks & Resets

  46. How to Write • Set USER_CMD to b’100 and Address on CLK180 • Wait for USER_CMD_ACK • Set the DATA and MASK on CLK90 • A dataword is double the memory interface • Provide BURST_LENGTH/2 datawords (BL=8  4 words) • Set the next address and data • Assert BURST_DONE on CLK180 after the last address • Deassert USER_CMD after BURST_DONE

  47. Read Address Burst Done Command Command Acknowledge Controller User Logic Read Data Data Valid Clocks & Resets Clocks & Resets

  48. How to Read • Set USER_CMD to b’110 and Address on CLK180 • Wait for USER_CMD_ACK • Set the next address • Assert BURST_DONE on CLK180 after the last address • Deassert USER_CMD after BURST_DONE • Watch for Data Valid to indicate when data is good (CLK90)

  49. Refresh Controller User Logic Auto Refresh Request Auto Refresh Done Clocks & Resets Clocks & Resets

  50. How to Refresh • At all times, check for auto refresh request (AR_REQ) in the CLK180 domain • If AR_REQ, then do not start a new transaction • Wait for AR_DONE (CLK180) • Go back to what you were doing

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