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CCC and TLU

André Welker Lennart Adam, Bruno Bauss , Volker Büscher, Reinhold Degele , Karl Heinz Geib , Sascha Krause, Yong Liu, Lucia Masetti, Phi Chau , Uli Schäfer, Rouven Spreckels , Stefan Tapprogge , Rainer Wanke. CCC and TLU. AIDA Meeting Frascati , 11. April 2013.

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CCC and TLU

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  1. André Welker Lennart Adam, Bruno Bauss, Volker Büscher, Reinhold Degele, Karl Heinz Geib, Sascha Krause, Yong Liu, Lucia Masetti, Phi Chau, Uli Schäfer, Rouven Spreckels, Stefan Tapprogge, Rainer Wanke CCC and TLU AIDA Meeting Frascati, 11. April 2013

  2. off-detector-electronic on-detector-electronic control, trigger, clock, busy Ethernet beam control • Mainz-development: • - firmware in VHDL • hardware • software Read-out-chain clock- andcontrol-card (CCC) fan-out more LDAs control clock trigger HBU analog digital data-aggregator (LDA) detectorinterface ASIC SiPM data busy DAQ PC Ethernet HBU analog digital detectorinterface ASIC SiPM André Welker, AIDA Meeting , Frascati, 11. April 2013 2

  3. off-detector-electronic on-detector-electronic control, trigger, clock, busy Ethernet beam control Read-out-chain clock- andcontrol-card (CCC) fan-out more LDAs control clock trigger HBU analog digital data-aggregator (LDA) detectorinterface ASIC SiPM data busy DAQ PC Ethernet HBU analog digital detectorinterface ASIC SiPM André Welker, AIDA Meeting , Frascati, 11. April 2013 2

  4. Requirements: • High clock stability in the whole detector • Configurationinterfaceover Ethernet • manage different runningmodes • forfeedbackfunctions • for beam control ClockandControlCard(CCC) • Status: • Builtandtestedfor a lab setupandused in testbeams 2012 • Next step: Upgrade forbiggertestbeams (almostfinished) André Welker, AIDA Meeting , Frascati, 11. April 2013 3

  5. Mezzanine on an Kintex 7 Evaluation-Board: FPGA-controlled CCC board: CCC atthetestbeam (front): 2012 ClockandControlCard CCC atthetestbeam (top): André Welker, AIDA Meeting , Frascati, 11. April 2013 4

  6. New 2013 ClockandControlCard First iteration with a Zynq-processor on a Zedboard for development: • Zedboard: • Evaluation Board • from Digilent • Zynq: • ARM9 dual core • processor (Linux) • + • - FPGA CCC Mezzanine from Mainz André Welker, AIDA Meeting , Frascati, 11. April 2013 5

  7. ClockandControlCard(CCC) Final design fortestbeams: • Peculiarityofthe • Mars-Modul: • Zynq • - ARM9 dual core • Linux + FPGA • 2. 512MB NAND/RAM 6U-VME formfactor front: top: Ethernet Micro-SD USER SYNC ASYNC TTL IN TTL OUT Mars-ZX3 firm:Enclustra André Welker, AIDA Meeting , Frascati, 11. April 2013 6

  8. 6U-VME Fan-out board: Fan-out board layout: Fan-out boardatthetestbeam: CCC Fan-out same as in 2012 André Welker, AIDA Meeting , Frascati, 11. April 2013 7

  9. Four main modes and 13 commands: signal: e.g. busy: conditions: ASIC bufferfull U Running Modes startacquisitionwithfallingedge stopacquisitionwithrisingedge 62 42 t André Welker, AIDA Meeting , Frascati, 11. April 2013 8

  10. off-detector-electronic on-detector-electronic busy control Ethernet beam control Read-out-chain - stopacquisition - andstartthedetectorread-out clock- andcontrol-card (CCC) fan-out bufferfull HBU analog digital data-aggregator (LDA) detectorinterface busy ASIC SiPM control DAQ PC Ethernet HBU analog digital detectorinterface ASIC SiPM control André Welker, AIDA Meeting , Frascati, 11. April 2013 9

  11. Four main modes and 13 commands: signal: e.g. busy: conditions: ASIC bufferfull U Running Modes startacquisitionwithfallingedge stopacquisitionwithrisingedge 62 42 t • extendedcommands: (backwardcompatible) • manualtrigger • listen on fallingorrisingedge • status • hard- andsoftreset • andmanymore André Welker, AIDA Meeting , Frascati, 11. April 2013 10

  12. Processing Instruction Configurator (piconf) (by RouvenSpreckels) • Configures all devices • Configurationproceduresareautomated • Everythingstored in oneor multiple XML files • Self-explanatory, predefined XML tags • Interface independent: • implemented: TCP/IP CCC and TLU Configuration André Welker, AIDA Meeting , Frascati, 11. April 2013 11

  13. piconfexample André Welker, AIDA Meeting , Frascati, 11. April 2013 12

  14. Two possibilities: • Baseline: Integratethecurrent TLU VHDL code • Fallback: Integrate a hardwarepartforthe Ethernet • Baseline: Integratea hardwarepartfortheEthernet • Fallback: Integratean own TLU VHDL code • Bothsolutionsdepends on thetimescale, lessmanpoweruntil • the May 2013 testbeam CCC with a TLU André Welker, AIDA Meeting , Frascati, 11. April 2013 13

  15. Onemodulephysicallyexists Hardware tested Firmware almostdone CCC shouldbereadytogoforthetest beam in May 2013 Status of CCC André Welker, AIDA Meeting , Frascati, 11. April 2013 14

  16. Thank you for your attention! André Welker, AIDA Meeting , Frascati, 11. April 2013

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