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Status of Tilecal upgrade activities at LPC

Status of Tilecal upgrade activities at LPC. ATLAS/LPC weekly meeting 27 June 2013 François Vazeille Roméo Bonnefoy (Technical coordinator). Summary of the LHC and ATLAS plans Summary of the Tilecal upgrade LPC activities. 1. Summary of the LHC and ATLAS plans.  LHC planning.

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Status of Tilecal upgrade activities at LPC

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  1. Status of Tilecal upgrade activities at LPC ATLAS/LPC weekly meeting 27 June 2013 François Vazeille Roméo Bonnefoy (Technical coordinator) • Summary of the LHC and ATLAS plans • Summary of the Tilecal upgrade • LPC activities 1

  2. Summary of the LHC and ATLAS plans  LHC planning Phase 0 Phase I Phase II = HL-LHC 5 (Peak) x 2 (Leveling) = 10 Integrated nominal Luminosity  > 3 000 fb-1 2

  3.  ATLAS Phase I 3

  4.  ATLAS Phase II ATLAS/LPC deeply commited 4

  5. Summary of the Tilecal upgrade Phase 0 : Laser II, Crack + MBTS Phase I : Gap/Crack Phase II : Electronics FE and BE + Gap/Crack • Making of a Demonstrator of the electronics for both FE and BE • - Validated at the surface (Building 175) then in the ATLAS test beam. • - Inserted in ATLAS in Phases 0 and I. •  Final design. Series production (during Phase I) then insertion (LS3). 5

  6. Insertion of production Drawers Drawer production Start Insertion of 1st Demonstrator Possibility of modifying or adding Demonstrators Insertion of 3 additional Demonstrators Stockholm upgrade meeting June 3, 2013 6

  7. LPC activities • Started in 2008 •  EoI, then LoI (Phase I ) and LoI (Phase II).  Reported in the ATLAS/LPC web site - Presentation of R&D studies http://atlas-clermont.web.cern.ch/atlas-clermont/satlas.html • LPC Documents (Talks, meeting reports, etc.) • https://indico.in2p3.fr/categoryDisplay.py?categId=219 • 6 LPC activities • - Laser II • - MobiDICK • - Mini-Drawers • - High Voltages • - PMT Dividers • - VFE and FE electronics (Tilecal Option 2) Reported today 7

  8. Mini-Drawers 8

  9.  Present ATLAS scheme Drawersholding VFE and FE electronics: - long (1.40 m) and heavy (42 kg) objects (512 Drawers), - associated in pairs ofSuper-Drawers (256 Super-Drawers), - electronically inter-dependent within a Super-Drawer. Alignment recovery of PMTs/cells Drawer Girder ring Alignment from outside 9

  10. sATLAS scheme  Mini-Drawers (half Drawer long). • Easier handling. • Easiest access in a restricted space. • Electronically independent. Alignment recovery Adjustable contacts Finger Basket Slider Drawer Adjustable contacts The Slider is ″supported″ in the rear part of Girder rings Alignment from inside 10

  11. Slider 2 Mini-Drawers Basket 1 Insertion of a Mini-Drawer inside a Basket, then in the Slider, then in a LB Module. Building 175 20 June 2013 11

  12. Tests at 45° Validation of the Mini-Drawer concept from tests at CERN, in various Tilecal module positions (0°, 45°, 90°) in agreement with theoretical calculations. [Tilecal week, 7 October 2011] + last tests at CERN June 20-21 Validation of the Slider concept from tests at CERN, using 3 Tilecal modules at 90° [Tilecal week, 28 September 2012] + last tests at CERN June 20-21 Slider 2 12

  13. Validation of the whole system: LB Module + Finger + Slider + Basket + 4 Mini-Drawers  last tests at CERN June 20-21 95 cm Possible working in a restricted space 13

  14. Next steps • Sharing of the mechanics activities • - Mini-Drawer bodies: Bucharest. • - Mechanical links, cooling…: Barcelona. • - Handling tools: Clermont-Ferrand. Supervised by LPC • Clermont-Ferrand works • improvements of the present Mini-Drawers and tools •  Demonstrator Option 1 “Chicago-Stockholm” tested in September. • - Improved Mini-Drawers. • - Slider version 3. • - Basket Version 2. • + latter studies (Special long Basket, Patch Panel…) • See yesterday Mechanics meeting • https://indico.in2p3.fr/conferenceDisplay.py?confId=8593 14

  15. High Voltages 15

  16.  Summary of previous progresses Several options reported by LPC since a long time HV regulation inside/outside Drawers [Tilecal meetings: February 2008, November 2009, September 2012]  Clermont-Fd proposition to develop an outside option but ready to provide all the information on the present ATLAS inside option. to Argonne and Lisbon. - Re-cycling of HV cards inside a special crate put in the electronics room. - Design of HV bus cards sharing the individual HV’s (with noise killers). - Use of multiconductor cables to supply the HV bus cards. 16

  17.  Present status HV Bus boards ready to equip 3 trains of Mini-Drawers A cable tray will run 3 different cable lengths towards Drawers 2, 3 and 4 (Fixation holes made here) 17

  18. Regulation crate HV Source Operational DCS Various cable lengths • 1 m long. • 4 times 20 m long (175) • 100 m long, to reproduce ATLAS. 18

  19. Tests in progress and planning  Clermont-Ferrand tests HV tests in progress, with a PMT Block lighted by a blue LED  Noise measurements for different cable lengths: going on.  CERN tests - Made the last week in the building 175  Mini-Drawer handling/connection tests  Insertion of the crate in arack of the electronics room • Next steps in 175 •  HV tests by LPC, once the Clermont-Fd tests will be fully efficient. •  Equipment of Demonstrator 1 “Chicago-Stockholm” by September . 19

  20. PMT Dividers 20

  21.  Summary of previous progresses •  Goal: To keep the Tilecal performances (Linearity, energy resolution) for the • measurement of very high energies at the highest luminosities. •  Proposed solution: Replacement of present “Passive Dividers” by • “Active Dividers” keeping stable the voltage repartition in between every stage •  Use of active components (Transistors and diodes) in the last 3 stages, • in order to balance the current stream induced by Minimum Bias events. •  Preliminary results previouslyshown [Tilecal meeting, 17 June 2011]. Passive Dividers Active Dividers 21

  22.  Main results given in the Tilecal Note (The Note ATL-COM-TILECAL-2013-014 is not yet approved) Passive Active Test Bench of batch of 10 Dividers • Pure electronics tests • using the upgraded Divider Test Bench •  Interdynode voltage comparisons • without/with injected currents of • 10 Passive and 20 Active Dividers. •  Protocol for the certifications of productions. • Full tests of Dividers behind PMTs •  Comparisons for a given AC light (Signal) • of 20 sets ″PMT-Passive Divider-Active Divider″ • in function of the injected DC light (Minimum Bias). No other BE electronics than a scope 22

  23.  Summary of results - The Passive Dividers fit the ATLAS specifications for Tilecal PMTs, but not fully for Crack scintillators(and so MBTS). - The Active Dividers fit the sATLAS specifications for both Tilecal and Crack scintillators (and MBTs), within a wide range going well above the expected Luminosities.  The linearity (and the energy resolution) will be improved /ATLAS.  They could equip all the PMTs. - The Divider Test bench has been upgraded and can welcome Passive/Active Dividers. • A batch of 350 Active Dividers has been produced • for the Crack/MBTS scintillators and the tests are in progress. You are invited to make a short visit of the test system ! 23

  24.  Last tests to do: radiation tests (Gammas, neutrons)  Special PCB to irradiate: active components within a square 7x7 cm2. • 20 Dividers: whole last 3 stages + resistors simulating the other ones. • 16 Transistors alone + 8 Diodes alone (with direct/inverted polarities). • Everything supplied at the right HV and on-line monitored. Resistors Diodes Last 3 stages Transistors PCB to be irradiated Power Supply  Complete Test bench on-line monitored PCB • Hardware ready. • Software almost ready + working tests to do. • Needs only the connection to a laptop • under labview. USB interface Mux/DAQ 24

  25. Front End electronics 25

  26.  Summary of previous progresses  Demonstrator option 2 A single link to the Back End electronics, with the maximum of functionalities inside a custom-made ASIC IBM 130 nm technology holding: - Current conveyors. - ADCs. - Digital integration for Cs calibration. - Part of CIS calibration (DAC outside).  FATALIC family - Based on 3-gain current conveyor associated to shaping stages - Tested at home, then at CERN. FATALIC 1 (June 2010) FATALIC 2 (December 2010) Tests at CERN (LED, Cosmics') [Tilecal week, 7 October 2011] FATALIC 3 (November 2011) Tests at CERN (Digital int.) [Tilecal week, 28 September 2012] 26

  27.  ADC: TACTIC project  Architecture - ”Classical” pipeline ADC architecture. - 12 bits resolution. - 40 Msamples/second. - Technology IBM 130 nm. - Submitted August 2012, received in February 2013. TACTIC 1 (1.8 x 1.8 mm2) Part of Test bench Tests in progress: static and dynamic tests • The chip is alive. • Progress must made on the Test bench. 27

  28.  Next steps and planning •  Signal/noise ratio and number of effective bits • from sinwave  Fourier analysis. •  Collaboration with IPHC Strasbourg on a 3in1 board • with FATALIC3 + TACTIC1 bounded directly on the PCB. •  In the fall, decision about the following step: • either a TACTIC2 or a complete FATALIC 4 chip ? • The major issue will be the funding.  Works in parallel - Final designs of 3in1 card (with DAC) and Mother Board 2. - Improvement of the digital integrator at the noise level: noises are different at home and at CERN: WHY ?  new tests at CERN are foreseen. - Decisions on the peaking time and on the shape (now not symmetrical)  simulations in progress, going up to the optimal filtering. 28

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