Innovative VLSI Design Replacing Ripple-Carry with Wallace-Tree Multipliers

Dec 14, 2025

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This work by Robert Gubitz and Bjoern Konieczek presents a new approach to VLSI design, focusing on replacing traditional ripple-carry adders with advanced ripple-lookahead adders. Additionally, we propose substituting carry-save array multipliers with Wallace-tree multipliers for enhanced performance. Our methods include rounding results to improve average error and present synthesis results of the designs. This study emphasizes the effectiveness of back-annotated design processes, showing promising advancements in VLSI implementation techniques.

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Innovative VLSI Design Replacing Ripple-Carry with Wallace-Tree Multipliers

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The second Design of Robert Gubitz and Bjoern Konieczek Applied VLSI Design
First Approach
New Approach Replace Ripple Look-Ahead Adder with Ripple-Carry Adder
New Approach Replace Carry Save Array Multiplier with Wallace-Tree
New Approach Rounding the Results to improve average Error
Resulting Design
Results – Synthesis
Results – Back-annotated Design
Thank YOU For YOUR ATTENTION

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 4 Sebastian Kruse. Design improvements. Mix of ripple carry and carry skip adders Bit size between 7 and 9 12 adders overall Some fixed bits. New optimizations for Synopsys.

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Applied VLSI Design

The third design of Robert Gubitz. Applied VLSI Design . Stage 2 design. Changes since Stage 2. Replace the remaining Carry-Save-Array multipliers with Wallace Tree multipliers Use term sharing for the multipliers Replace Ripple-Carry adders with Carry-Skip look-ahead adders

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Applied VLSI design – Phase 1

Applied VLSI design – Phase 1. Martin Kittel Sebastian Stieber. Our design. Multiplier: 17 x 22 bit Pezaris array multiplier 22 bit signed coefficients 16 bit unsigned pixel value + 1 sign bit (‘0‘) Adder: 39 bit ripple carry adder 1 halfadder 38 fulladder. Multiplier.

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 4 Martin Kittel. Results Phase 3. Slansky Adder Pipeline Depth = 5. Improvements. No changes in the Design Cadence Encounter Aspect Ratio 1:1 has highest frequency

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Changes across technologies Results of Phase 5 Andy Schellin. Fundamentals. Why changing manufacturing technology? Functionally reasons Economically reasons Lower Voltage Higher frequency. Power Loss. Problems.

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Adder structures Sebastian Kruse. Types of adders. Redundant Carry-Save (CSA) Redundant-Binary (RBA) Not redundant (CPA) Ripple-Carry (RCA), Manchester-Carry-Chain (MCC)

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 4 Andy Schellin. Tasks/Workflow. Optimization of Synopsys results Layout Floorplanning , Placement, Routing Improvements. Floorplanning. Best Metric. Cadence Layout. Aspect-Ratio: 3

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. ASIC design for an RGB  YCbCr -transformation Results of Phase 4 Florian Ludwig. Parallel prefix adders. Sklansky adder Regular and small area Large fan-out Kogge-Stone adder Minimum logic depth Minimum fan-out

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Applied VLSI Design

The second Design of Robert Gubitz and Bjoern Konieczek. Applied VLSI Design. First Approach. New Approach. Replace Ripple Look-Ahead Adder with Ripple-Carry Adder. New Approach. Replace Carry Save Array Multiplier with Wallace-Tree. New Approach.

297 views • 9 slides

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design. Jacob Maxa Results of Phase 3: ST65 Netlist 13.12.2012. Institute MD, University of Rostock. Challenge. Create a Verilog netlist for the ST65 technology Build upon NAND/NOR gatter 65 nm structure width

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 3 Nam Pham Van. Change of coefficient. Reduce an addition to one shift operation On FPGA no noticeable influence On VLSI noticeable power reduction. Design assumption. Benchmark:.

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. FPGA design for a RGB  YCbCr -transformation Results of Phase 2 Philip Grunert, Florian Ludwig. Results of Phase 1. Optimization of the multiplier. [1]. Average Error. Rounding Offset. 20. 3. 36. 2. 1. 21.

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Phase 2 Robert Balla und Henning Puttnies. Institute MD, University of Rostock. Implementation. Special multipliers 1-Operand-Multiplier (generic Value) CSD-Recoding Carry-Save-Adders with T≠O(n)

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Applied VLSI Design

The third Design of Bjoern Konieczek. Applied VLSI Design. Design Approach. G. R. B. R. G. B. Y. Cb. Cr. Carry Skip Look-Ahead Adder. Replace Ripple-Carry Adder with Carry Skip Look Ahead Adder. Wallace Tree. Replace Carry Save Array Multiplier with Wallace-Tree. Rounding.

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design. Jacob Maxa Results of Phase 4: Chip Layout 10.01.2013. Institute MD, University of Rostock. Challenge. Create a fully working chip layout Redo the same task with additional I/O pads Ideas

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 1 Eike Schweißguth, Arne Wall. Institute MD, University of Rostock. Choice of Adder Architecture. Normalized Gate Delay x Gate Count. [1]. Adder Architecture - Carry Increment Adder.

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Differences between FPGA and ASIC René Romann. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock. Slide 1. Overview. FPGA vs. ASIC

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 2 Jens Rudolf & Johannes Lange. Retrospection. Layout two weeks ago. Current Layout: Implemented Truncation of Bits Carry Save Adder Pipelining Rejected Wallace Booth Algorithm.

251 views • 8 slides

Applied VLSI Design

The first Design of Robert Gubitz and Bjoern Konieczek. Applied VLSI Design. First approach. Replace equations with a Calculation Unit. Calculation Unit. Calculation Unit (modified). Ripple-Carry-Look-ahead-Adder. Second Approach - Enhancement.

292 views • 9 slides

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 4 Robert Mars. Expected Differences. frequency ↓ due to wire delay power ↑ due to wire capacitance Considered Floorplan optimizations : Aspect Ratio Utilization. Aspect Ratio.

208 views • 8 slides

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Course and contest Results of Phase <3> <Ayad Mostafa>. Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Slide 1. Design and architecture 1. Adders: Carry Lookahead Adder (CLA) Fast Optimization Reduced foot print by limiting addition to 4-bits per stage

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 3 Sebastian Kruse. Optimizations. Change of coefficent Now no adder is needed for calculation Look for higher metric at lower voltage area Comparison between different adder types.

237 views • 9 slides

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