3D Track Trigger Module R&D Status

1. 3D Track Trigger Module R&D StatusRon Lipton, Fermilab Subjects: • Introduction • VICTR 3D Chip and Multiproject Run • Mating sensor design and fabrication • Oxide bonding • Interposer Development and Bump Bonding • Carbon fiber properties • Temperature profiles • Chip and module logic and data flow • Mass calculations No discussion of thoughts on trigger architecture, system design, simulation issues

2. 3D Module Concept About a year ago we proposed a Pt module R&D program based on emerging 3D IC technology. The technology provides the ability to directly connect both the top and bottom of a readout IC to sensors above and below • Signals from the top sensor can be correlated locally to signals from the bottom – no encoding/decoding of hit addresses • Clusters can be found locally • A single layer of chips can be used for two layers of sensors • Z pitch is limited only by power and electronics density – good primary vertex resolution A number of problems have to be solved • Demonstration of 3D chips • Demonstration of sensor integration and thinning • Development of a low mass interposer • Plausible system design including chip logic, data volumes, and power consumption • Demonstration of bump bonding

3. Module Layout Demonstration module Full module

4. Sensor VICTR Chip 3D interconnectivity is enabled by “through-silicon vias” on the IC • This capability was made available on the 2009 Fermilab-sponsored 3D multiproject run at Tezzaron/Chartered • VICTR is a demonstrator chip intended for 3D sensor integration • Front end uses ATLAS FEI4 design. • Simple top-bottom coincidence, serial readout Submission was a learning experience for Fermilab as a silicon broker • Different Chartered offices provided different design kits for different labs • Chartered frame size misunderstood • Software errors in Micromagic • Errors in Charted fill obscuring targets • Real errors in subreticules – missing, extra or misused layers • … Best guess for delivery is now end of June Interposer Bump Bond module Sensor

5. Industrialization • Discussions have begun on offering commercial 3D multiproject runs • Collaboration of CMC (Canada), CMP (Europe) and MOSIS (US) • Tezzaron will be the initial manufacturer • The goal is to have the simple kit ready by June so that CMP/MOSIS/CMC can make a general announcement that they are now offering 3D MPW runs. One can expect at least 2 per year. Very positive development, more runs, more professional, focussed 3D design kits (pixel, digital, analog/digital tiers)

6. Sensor integration • We are planning to bond the VICTR IC to the sensor and thin to expose the TSV using the DBI oxide bonding process • Good yields require controlled topography on the sensor • Sensor fabrication underway at BNL with thin metal and oxide layers to optimize DBI process yield • First batch (July) to test planarity, backside protection, warp • Second batch (Sep) for bonding to readout ICs Test structures Long strip short strip Imaging ILC

7. Oxide Bonding • Verified DBI performance with BTeV Chip • X-ray source tests • Radiation tests to 10 Mrad • Tests at FNAL test beam • We are working closely with Ziptronix to optimize the bonding process/yield • Tight requirements on sensor topology limit sensor fabrication (thin layers) • We will use some of the pre-series wafers to explore wafer post processing • Thick oxide deposit • Tungsten sputtering • Chemical-mechanical polish • This should allow a “generic” wafer to be used for DBI

8. Interposer and bump bonding • Test interposers fabricated at Cornell Nanofabrication facility • 600 micron pitch x 0.5 mm Silicon based interposers will be delivered to UC Davis soon. • Test PC boards ready • Will test bonding using gold and solder bumps • Final (600 x 640 mm) silicon interposers will be fabricated this summer • UCD will try both gold and solder bump bonding • Parallel R&D starting on PC based interposers, removing material by etching or drilling

9. Kapton PC-Based Design Data bus (2 layers) Neighbor bumps Analog via array 600 micron pitch 9.6 cm Data bus (2 layers) Material Removed away from through vias 10 cm

10. Red 15 deg Black 75 deg Blue 50 deg Cyan copper Mechanical R&D (Cooper, Johnson) Carbon fiber electrical properties (M. Johnson) • Understand electrical shielding/grounding • 6 ply K13C2U samples ~ 4” x 9” x 0.0133” were prepared with lay-ups consistent with proposed rod structures • Ply angles (degrees) with respect to long. direction • 0, 75, -75, -75, 75, 0 • 0, 60, -60, -60, 60, 0 • 90, 15, -15, -15, 15, 90 • DC results: 71, 77, 41 milli-Ω • Based on laminate theory, the ratios of resistances should be 72.4, 73.8, 44.1 milli-Ω • End-to-end resistance of a 2.8 m long rod box including the core flanges should be roughly 0.20 Ω. • Similar structures have often been said to have an end-to-end resistance ~ 10 Ω. Our guess is that the higher values were the resultof poor contact to the carbon fiber.

11. Mechanical (Cooper) Module cooling – hand calculations • Estimate is based on 3.4 W per module half-length and 80% DC-DC conversion efficiency • Power into one cooling tube is 3.4 W / 2 / 0.8 / 100 mm = .02125 W/mm. • Over a tube length of 5600 mm, power is 119 W. • Temperature change < 2.7o C over the length of a cooling tube with an average cooling tube temperature of -20o C. Module Temperature • Conduction from the cooling tube inner wall to the start of the core flange contributes a temperature increase of ~ 10.6o C. • ΔT through the module thickness is small (0.69o C) - ROIC’s placed so that their power does not pass through the interposer.

12. Chip Logic • 3D design allows for local logic • Each strip looks at ~ 4 neighbors • Kill all hits if cluster is too large • Central strip outputs hit information to internal logic • Interpolation to ½ strip • External settings for dead or noisy strips, shift of information in phi, pt threshold • Neighbor chip sends cluster information for last short strips • Pipelined design: • Signal amplification/discrimination • Local cluster finding • Global cluster finding • Pt and charge outputs • Z clustering? • Event buffer with hits or clusters

13. Module Data Flow 100 MHz x 22 bits • Micropipelined data transfer between chips – all data transferred up or across in 25 ns • Tri state possible? – probably not • Event data (5%) appended to trigger data • Can be configured to use 1/2 , 1 or 2 GBT/module • Design of VHDL simulation begun at FNAL – looking at various pipeline architectures • May want pipeline test chip to understand SEU sensitivity ~20 MHz x 22 bits/column Support rod ROIC ½ sensor GBT Flex circuit Ronald Lipton 4/28/2010

14. Material Budget calculations (Spiegel) Estimate material budget in a particular implementation of a doublestack module based on 3D integration of sensor and readout chips along the lines of the current Tezzaron/Chartered R&D project • A light, ~1mm gap interposer for connecting sensors and providing connections through bump bonding (Alexander, Tripathi) • Rod-based mechanical design described previously (Cooper) • Ideas on triggering and readout (Johnson, Heinz) • Simulation studies at S-LHC rates (Fields, Ryd, and others) The goal is to be aggressive in the design of pT layers so as to limit the amount of material. For example • Use of copper mesh integrated into CF for grounding and polyimide HDI technology from D0 Run II Layer 0 project • Decreasing the density of GBT’s and DC-DC convertors for |Z|>Z_critical based on simulation studies. • Reduce GBT functionality to what is absolutely essential – uni- directional, minimal error checking

15. Material Budget II • Focus on the material in a single double-stack layer near η=04 (x2) 10cm x 10cm sensors • Assume • 4 GBTs and 4 DC-DC convertors for |z| < 120 cm • 2 GBTs and 2 DC-DC convertors for |z| > 120 cm • The above numbers are for a single layer (double stack) near η=0. • Four layers of 200 μm thick silicon, etc. • 3.4 RL/double stack • There are still several features to add – other electrical components, wires (HV, laser), fibers, mechanical supports, and we also need to reconcile some differences with the pT layer descriptions developed for the modeling tool. Still the initial look is not discouraging. Ronald Lipton 4/28/2010

16. Conclusions No time for conclusions , so just consider the alternate circuit during questions