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University of Connecticut

University of Connecticut. Virtual Lab Carl DiFederico , Shane Tobey, Kasim Ward Graduate Student Advisor: Qihang Shi Senior Faculty Advisor: Mohammed Tehranipoor Electrical & Computer Engineering. Table of Contents. Project Overview Abstraction of Module 1 (Hardware)

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University of Connecticut

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  1. University of Connecticut Virtual Lab Carl DiFederico, Shane Tobey, Kasim Ward Graduate Student Advisor: Qihang Shi Senior Faculty Advisor: Mohammed Tehranipoor Electrical & Computer Engineering

  2. Table of Contents • Project Overview • Abstraction of Module 1 (Hardware) • Abstraction of Module 2 (Software) • Hardware Model and Requirements • Software Model and Requirements • Upcoming Deadlines

  3. Hardware Model and Requirements • The current hardware model includes replicating the current first generation board into a total of 10-20 boards • We have found some problems with the first generation board, namely fragility. The wires need to be more secure. • We will create an array of boards with a modular mounting bracket/base. • The boards will be connected to the server by a modular bus. The bus will communicate with a microcontroller that dictates which board is enabled for input. • We also need to switch the output to the oscilloscope, i.e. connect the oscilloscope probe to the bus

  4. Hardware Model and Requirements • Fig. Proposed Hardware Model

  5. Hardware Model and Requirements • Hardware Requirements/ Items to be bought: • Boards • Brackets • Bus Interface • Microcontroller to switch between boards • Use of spare computer to be reformatted as a dedicated server, or a new computer

  6. Software Model and Requirements • The software portion of the project will entail changes in the code to support 10-20 boards • Python code must be modified to allow for dynamic changes in voltage specifications for leakage test (for within a tolerance) • The server will use Microsoft Server OS (free for students) • The server must store the identifier of each chip and the engineer must put each identified chip in the correct slot • A Microcontroller must be programmed to select along the bus

  7. Upcoming Deadlines and Goals • Make the First Generation Board wiring more secure • Parts research • Sep 23 (M) Project Statements Due • Sep 30 (M) Project Specifications Due

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