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“FPGA shore station demonstrator for KM3NeT”. by K. Manolopoulos , A. Belias and B. Koutsoumpos NESTOR Institute - NOA Presenting for the KM 3 NeT Consortium: Kostas Manolopoulos. KM3NeT Readout Concept. KM 3 NeT: Deep sea neutrino telescope More than 10,000 optical modules
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“FPGA shore station demonstrator for KM3NeT” by K. Manolopoulos, A. Belias and B. Koutsoumpos NESTOR Institute - NOA Presenting for the KM3NeT Consortium: Kostas Manolopoulos
KM3NeT Readout Concept • KM3NeT: • Deep sea neutrino telescope • More than 10,000 optical modules • Point to point optical network • Numerous optic fiber channels arriving at the shore station VLVnT 11
Resulting Requirements • Shore station requirements: • Receive incoming data • Perform merging and time ordering • Send data to DAQ system • Transmit necessary commands to the optical modules VLVnT 11
Overall Readout Scheme • All digitized data sent to shore • Expected rate > 100Gbps • Real-time processing • Bidirectional functionality • Asymmetric physical channel allocation
KM3NeT Demonstrator • 4 Digital Optical Modules (DOMs) • Convert measurements to digitized data • Transmit them embedded in an Ethernet frame to the shore • Shore station • collects incoming data • issues commands to DOMs VLVnT 11
Readout Electronics on Shore • Main functions: • Ethernet point to point data reception • Ethernet broadcasting data distribution • Clock & Synchronous Command distribution • Time measurement of the optical network for each point (calibration) • GPS reference time stamping interface VLVnT 11
PCI / FMC connections SMA cable RJ45 Ethernet cable SC link (I2C) Ethernet cable Shore Station Functional diagram Optical Network Ethernet Switch Rx Tx Rx Tx Optical Domain Rx Tx Rx Tx ML605 Rx Tx Rx Tx DAQ Rx Tx Rx Tx SMA SFP see talk by Jelle Hogenbirk see talk by AnvarShebli ML507 GPS & Clock services
TEMAC TEMAC TEMAC TEMAC TEMAC TEMAC TEMAC TEMAC ML605 Block diagram Buffer Clk & Cmd Insertion Buffer GTX Buffer Clk & Cmd Extraction Buffer GTX Clk & Cmd Extraction GTX GTX Clk & Cmd Insertion GTX GTX Clk & Cmd Insertion GTX GTX Time system (Counter, etc..) Clk &Command Control Master clock VLVnT 11
Xilinx ML605 Evaluation Board VLVnT 11
ML605 Characteristics • FPGA: VIRTEX 6 LX240T-1 • Communications & Networking • 10/100/1000 Tri-Speed Ethernet (GMII, RGMII, SGMII, MII) • SFP transceiver connector • GTX port (TX, RX) with four SMA connectors • 4 hard TEMAC cores
ML605 Characteristics • 20 GTX Multi Gigabit Transceivers • 8 MGTs wired to PCIe • 8 MGTs wired to FMC HPC connector • Clocking resources • 200 MHz Oscillator (Differential) • SMA Connectors for external clock (Differential)
PCI Express Expansion Module VLVnT 11
Quad SFP Transceiver VLVnT 11
Xilinx ML507 Evaluation Board VLVnT 11
ML507 Characteristics • FPGA: Virtex 5 FX70T-1 • Programmable system clock generator • 10/100/1000 Tri-Speed Ethernet • PCIe with 1 GTP/GTX • SFP transceiver connector with 1 GTP/GTX • Same processor as in DOMs • Runs DAQ software in VxWorks • (see talk by Frederic Louis) VLVnT 11
Conclusions • So far we have: • developed an architecture for data gathering and broadcasting • evaluated FPGA based platform systems for the shore station • full-chain test coming up • What next? • Adapt the existing scheme to actual KM3NeT scale • Enhance it with respect to flexibility and scalability VLVnT 11
