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COMP541 Flip-Flop Timing

COMP541 Flip-Flop Timing. Montek Singh Feb 23, 2010. Topics. Lab: Feedback VGA Display Timing Generator Timing of flip-flops Timing analysis of sequential systems Clock skew. Input Timing Constraints.

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COMP541 Flip-Flop Timing

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  1. COMP541Flip-Flop Timing Montek Singh Feb 23, 2010

  2. Topics • Lab: • Feedback • VGA Display Timing Generator • Timing of flip-flops • Timing analysis of sequential systems • Clock skew

  3. Input Timing Constraints • Setup time: tsetup = time before the clock edge that data must be stable (i.e. not changing) • Hold time: thold = time after the clock edge that data must be stable • Aperture time: ta = time around clock edge that data must be stable (ta = tsetup + thold)

  4. Output Timing Constraints • Propagation delay: tpcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) • Contamination delay: tccq = time after clock edge that Q might be unstable (i.e., start changing)

  5. Dynamic Discipline • The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge. • Specifically, the input must be stable • at least tsetup before the clock edge • at least until thold after the clock edge

  6. Implications on Design • The delay between registers (clock period and rate) has a minimum and maximum delay, dependent on the delays of the circuit elements • Both CL and FFs

  7. Setup Time Constraint • Setup time constraint depends on max delay from R1 through the combinational logic. • And input to R2 must be stable at least tsetup before the clock edge. • What’s min clock period? What’s Tc? Tc ≥ tpcq + tpd + tsetup tpd ≤ Tc – (tpcq + tsetup) • So, clock period constrained by: • Delay in CL • Delay in previous regs • Setup requirement of R2

  8. Hold Time Constraint • Hold time constraint depends on the minimum delay from register R1 through the combinational logic. • The input to R2 must be stable for at least thold after the clock edge. thold < tccq + tcd tcd > thold - tccq

  9. Timing Analysis Timing Characteristics tccq = 30 ps (FF contamination) tpcq = 50 ps (FF propagation) tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tpd = tcd = Setup time constraint: Tc≥ fc = tpd = 3 x 35 ps = 105 ps tcd = 25 ps Setup time constraint: Tc≥ (50 + 105 + 60) ps = 215 ps fc = 1/Tc = 4.65 GHz Hold time constraint: tccq + tpd > thold ? Hold time constraint: tccq + tpd > thold ? (30 + 25) ps > 70 ps ? No!

  10. Fixing Hold Time Violation Add buffers to the short paths: Timing Characteristics tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tpd = 3 x 35 ps = 105 ps tcd = 2 x 25 ps = 50 ps Setup time constraint: Tc≥ (50 + 105 + 60) ps = 215 ps fc = 1/Tc = 4.65 GHz Hold time constraint: tccq + tpd > thold ? (30 + 50) ps > 70 ps ? Yes!

  11. Hold Time • Often FFs are designed for a hold time of zero • To avoid these tricky problems

  12. Clock Skew • Clock doesn’t arrive at all registers at the same time • Skew is the difference between two clock edges • Examine the worst case: • guarantee that discipline is not violated for any register • many registers in a system!

  13. Setup Time Constraint with Clock Skew Worst case: CLK2 is earlier than CLK1 Tc ≥ tpcq + tpd + tsetup + tskew tpd ≤ Tc – (tpcq + tsetup + tskew)

  14. Similar Issue w/ Hold Time • We won’t go over example • Have a look in book

  15. Next Time • Read Section 3.5 • Metastability • Then we’ll move on to memories • Section 5.5 • Homework 3 due

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