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USB Eye program under u-boot

USB Eye program under u-boot. Port Test Modes. • Refer to P2040RM in Chapter 16.9.13 Port Test Modes • It’s also work on other Freescale PPC. • EHCI host controllers implement the port test modes Test J_State, Test K_State, Test_Packet, Test Force_Enable, and Test SE0_NAK as described

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USB Eye program under u-boot

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  1. USB Eye program under u-boot

  2. Port Test Modes • • Refer to P2040RM in Chapter 16.9.13 Port Test Modes • • It’s also work on other Freescale PPC. • • EHCI host controllers implement the port test modes Test J_State, Test • K_State, Test_Packet, Test Force_Enable, and Test SE0_NAK as described • in the USB Specification Revision 2.0. The required, port test sequence is • (assuming the CF-bit in the CONFIGFLAG register is set): • • In demo board CCS bar in FE000000 • • USBDR Controller- Block Base Address 0x21_0000(USB1)/0x21_1000(USB2)

  3. Port Test Modes -cont. • 1. Disable the periodic and asynchronous schedules by clearing the USBCMD[ASE] and USBCMD[PSE]. • 16.5.7 USB command (USBx_USBCMD) Base address + 140h offset CCSR bar + USB offset 0x21_0000 + USBCMD 0x140 You need plug any USB device first. =>usb start =>md 0xfe210140 1 fe210140: 010b0800 <byte swap> 00080b01 <modify ASE/PSE> 00080b01 <byte swap back> 010b0800 =>mw 0xfe210140 010b0800

  4. Port Test Modes -cont. • 2. Place all enabled root ports into the suspended state by setting the Suspend bit in the PORTSC register (PORTSC[SUSP]). • 16.5.18 Port status/control (USBx_PORTSC) Base address + 184h offset =>md 0xfe210184 1 fe210184: 1010009c <byte swap> 9c001010 <modify SUSP > 9c001090 <byte swap back> 9010009c =>mw 0xfe210184 9010009c

  5. Port Test Modes -cont. • 3. Clear USBCMD[RS] (run/stop) and wait for USBSTS[HCH] to transition to a one. Note that an EHCI host controller implementation may optionally allow port testing with RS set. However, all host controllers must support port testing with RS cleared and HCH set. • 16.5.8 USB status (USBx_USBSTS) Base address + 144h offset Clear USBCMD[RS] =>md 0xfe210140 1 fe210140: 010b0800 <byte swap> 00080b01 <modify Run/Stop> 00080b00 <byte swap back> 000b0800 =>mw 0xfe210140 000b0800 wait for USBSTS[HCH] to transition to a one =>md 0xfe210144 1 fe210144: 88100000 <byte swap> 00001088 <if HCH is one> 00001088 <byte swap back> 88100000 fe210144 should be 88100000

  6. Port Test Modes -cont. • 4. Set the Port Test Control field in the port under test PORTSC register to the value corresponding to the desired test mode. If the selected test is Test_Force_Enable, then USBCMD[RS] must then be transitioned back to one, in order to enable transmission of SOFs out of the port under test. =>md 0xfe210184 1 fe210184: 1010009c <byte swap> 9c001010 <modify PTC > 9c011010 <byte swap back> 1010019c =>mw 0xfe210184 1010019c Set USBCMD[RS] =>md 0xfe210140 1 fe210140: 000b0800 <byte swap> 00080b00 <modify Run/Stop> 00080b01 <byte swap back> 010b0800 =>mw 0xfe210140 010b0800

  7. Port Test Modes -cont. • 5. When the test is complete, system software must ensure the host controller is halted (HCH bit is a one) then it terminates and exits test mode by setting USBCMD[RST]. Follow the first step. External Flash Programmer

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