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Introduction to Verilog HDL and Hardware Description Language Design

This article provides an introduction to Verilog HDL and hardware description language design, covering structural, behavioral, and data flow descriptions.

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Introduction to Verilog HDL and Hardware Description Language Design

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  1. 九十一學年度國立高雄應用科技大學 IC設計研習班 硬體描述語言設計 92.3.1 蔣元隆 撰

  2. 1. Verilog HDL Introduction (1) Two HDLs (Hardware Description Language) under IEEE Standards • Verilog HDL: IEEE 1364, • VHDL (Very High Speed I.C. HDL): IEEE 1164 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  3. 1. Verilog HDL Introduction (2) Types of Descriptions: • Structural Descriptions – describes the connection of a circuit, i.e. net-list. • Behavioral Descriptions – describes the function of a circuit including always block, initial block, function, task. • Data Flow Descriptions (or Register Transfer Level RTL Description) -- describes the function using assignment, 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  4. 1. Verilog HDL Introduction (2-1) • Any type of descriptions can be mixed in a module such as the following figure. module name(port1,port2,…); Input, output and variable declarations always block1 Structural descrition Assign statement always block2 endmodule 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  5. 1. Verilog HDL Introduction (3) • Behavioral Description module D_FF(q, d, clk, reset); output q; input d, clk, reset; reg q; always @(posedge reset or negedge clk) if (reset==1’b1) q=1’b0; else q=d; endmodule 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  6. 1.Verilog HDL Introduction (4) An Example of Structural Description `include “D_FF.v” module T_FF (q1, clk1, reset1); output q1; wire q1, d1; input clk1, reset1; D_FF dff0(.q(q1), .d(d1), .clk(clk1), .reset(reset1)); not n1(d1, q1); endmodule q1 d1 q d clk1 clk reset reset1 Instantiation 實體化 實體化 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  7. 1.Verilog HDL Introduction(4) • What is the structural description of the following circuit ??? module dummy(a,b,c,d,g); a input a,b,c,d; e u1 g b output g; u3 c wire e,f; f u2 d and u1(e, a, b); and u2(f, c, d); or u3(g, e, f); endmodule 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  8. • module dummy_2(a, b, c, d, e, f, g, h, k); • input a,b,c,d,e,f,g,h; • output k; • wire L,M; • dummy u1(a, b, c, d, L); • dummy u2(e, f, g, h, M); • and u3 (k,L,M); • endmodule U1 u3 U2

  9. 1.Verilog HDL Introduction (5) • What is the structural description of the following circuit: Ripple Carry Counter ?? q[0] q[1] q[2] q[3] q q q q clk clk clk clk clock reset reset reset reset reset 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  10. 1.Verilog HDL Introduction (6) `include “T_FF.v” module ripple_carry_counter(q, clock, reset); output [3:0] q; wire [3:0] q; input clock, reset; T_FF tff0 (q[0], clock, reset); T_FF tff1 (q[1], q[0], reset); T_FF tff2 (q[2], q[1], reset); T_FF tff3 (q[3], q[2], reset); endmodule 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  11. 1.Verilog HDL Introduction (7) initial begin reset=1’b1; #15 reset=1’b0; #180 reset=1’b1; #10 reset=1’b0; #20 $finish; end initial $monitor($time,”output q= %d”, q); endmodule • Test Bench `include “ripple_carry_counter.v” module stimulus; reg clk, reset; wire [3:0] q; ripple_carry_counter r1(q,clk,reset ); initial clk=1’b0; always #5 clk=~clk; 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  12. 1.Verilog HDL Introduction (7-1) #180 reset=1’b1; #10 reset=1’b0; #20 $fclose(handle); $finish; end initial begin handle=$fopen(“rcc.out”); desc=handle | 1; $fmonitor(desc, $time,”output q= %d”, q); end endmodule `include “ripple_carry_counter.v” module stimulus; reg clk, reset; wire [3:0] q; integer handle, desc; ripple_carry_counter r1(q,clk,reset ); initial clk=1’b0; always #5 clk=~clk; initial begin reset=1’b1; #15 reset=1’b0; 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  13. 1.Verilog HDL Introduction (8) • The results after running test bench 120 output q= 11 130 output q= 12 140 output q= 13 150 output q= 14 160 output q= 15 170 output q= 0 180 output q= 1 190 output q= 2 195 output q= 0 210 output q= 1 220 output q=2 0 output q= 0 20 output q= 1 30 output q= 2 40 output q= 3 50 output q= 4 60 output q= 5 70 output q= 6 80 output q= 7 90 output q= 8 100 output q= 9 110 output q= 10 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  14. 1.Verilog HDL Introduction (9) • Wave form Time 0 5 10 15 20 30 ………………………………190.195……210 220 225 …… clock reset Counter 0 1 2 3 4 ……………2 .0 1 2 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  15. 1.Verilog HDL Introduction (10) • Data Flow Descriptions (Continuous Assignment) Example: assign sum=a^b^cin; // always @ (a or b or cin) // sum=a^b^cin; assign cout=(a&b) | (a&cin) | (b&cin); Where &: and, |:or, ^:xor. sum and cout should be wire type variables. 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  16. 1.Verilog HDL Introduction(11) • First Project Design a Verilog description and testbench for a 4-bit adder . Hint: Hierarchical level Full Adder 4-bit Adder 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  17. 1.Verilog HDL Introduction(12) • Full Adder Module module fadder(a, b, cin, sum, cout); input a, b, cin; output sum, cout; assign sum = a ^ b ^ cin; assign cout = (a &b) | (a&cin) | (b & cin); endmodule • 4-bit adder ?? • Test Bench ?? 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  18. 1.Verilog HDL Introduction(12-1) a[3] b[3] a[2] b[2] a[1] b[1] a[0] b[0] `include “fadder.v” module adder4 (a, b, cin, sum, cout); input [3:0] a, b; input cin; output [3:0] sum; output cout; wire [2:0] c; fadder fa0(a[0], b[0], cin, sum[0], c[0]); fadder fa1(a[1], b[1], c[0], sum[1], c[1]); fadder fa2(a[2], b[2], c[1], sum[2], c[2]); fadder fa3(a[3], b[3], c[2], sum[3], cout); endmodule fa3 fa2 fa1 fa0 c[2] c[1] c[0] cout cin sum[3] sum[2] sum[1] sum[0] assign {cout, sum}=a+b+cin; 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  19. 1.Verilog HDL Introduction(12-2) for (i=0; i<=5‘d15; i=i+1) begin a=i; for(j=i; j<=5‘d15;j=j+1) begin b=j; #5 $display ($time, “a=%d, b=%d, cin=%b, sum=%d, cout=%b”, a, b, cin, sum, cout); end end cin=~cin; end //repeat $finish; end //initial endmodule `include “adder4.v” module st_adder4; reg cin; wire [3:0] sum; reg [3:0] a, b; reg [4:0] i,j; //integer i, j; wire cout; adder4 u1 (a, b, cin, sum, cout); initial begin cin=0; repeat(2) begin sel=0; repeat (2) begin sel=~sel; end 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  20. 1.Verilog HDL Introduction(12-3) `include “adder4.v” module st_adder4; reg cin; wire [3:0] sum;wire cout; reg [3:0] a, b; integer i, j, handle, desc; adder4 u1 (a, b, cin, sum, cout); initial Begin handle=$fopen(“adder4.out”); desc=handle |1; cin=0; repeat(2) begin for (i=0; i<=‘d15; i=i+1) begin a=i; for(j=i; j<=‘d15;j=j+1) begin b=j; #5 $fdisplay (desc, $time, “a=%d, b=%d, cin=%b, sum=%d, cout=%b”, a, b, cin, sum, cout); end end cin=~cin; end //repeat $finish; $fclose(handle); end //initial

  21. 2. Verilog Basic Concepts(1) • Comment: // or /* and */ • Blank space: \b • Tabs:\t • Newlines: \n • Number Specification: sized: 4’b1010, 12’habc, 16’d255,6’o77 unsized: 2345 //32 bits decimal value ‘hc3 //32 bits Hex. Value ‘o21 // 32 bits Oct. value 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  22. 2. Verilog Basic Concepts(2) • Binary values 0: low voltage 1: high voltage x : unknown value z : High Impedence Examples: 12’h13x, 6’hx, 32’bz Case (in) 8’b1xxxxxxx: out=3’b000; 8’b01xxxxxx: out=3’b001; 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  23. 2. Verilog Basic Concepts(3) • Negative number: -8’d35 • Underscore :12’b1111_0101_1100 • Question mark: 4’b10?? //same as 4’b10zz • String: “Hello! How are you?” 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  24. 2. Verilog Basic Concepts(4) • Nets wire: declare a net wand: declare a wired and net wor: declare a wired or net tri, trior, trireg, triand,tri0, tri1: not implemented by Synopsis Synthesizer 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  25. 2. Verilog Basic Concepts(5) • Registers: Keyword “reg” is used to declare a variable which will be assigned a value in a behavioral description, i.e., in the left hand of an assignment inside the always block. Example: a should be declared as a reg variable reg a; …. always @ (….) a=….. ; 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  26. 2. Verilog Basic Concepts(6) • Vectors: Declarations: wire [3:0] bus; reg [7:0] v_address; References: bus[3]=…..; K=v_address[5]& ….; 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  27. 2. Verilog Basic Concepts(7) • Integers integer counter; reg [7:0] counter; // declare a 32 bit variable with a positive // or negative value, while reg is used to // declare an unsigned variable. 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  28. 2. Verilog Basic Concepts(8) • Real Numbers: “real” is not implemented by synthesizer • time: for simulation only. Used to declare a time variable: Example: time save_sim_time; // declaration initial save_sim_time=$time; //reference 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  29. 2. Verilog Basic Concepts(9) • Arrays Declarations: reg [4:0] port_id[0:7]; // declare an 8-element array port_id with 5 bits per element. X port_id[2][3]= …….; V port_id[2]=5’b01010; reg count [0:7]; // declare an array count with 8 elements with 1 bit per element; 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  30. 2. Verilog Basic Concepts(10) • Arrays (cont.) References: port_id[4]=K; // K has been declared //as a 5-bit reg. The K’s value is //assigned to 4thelement of port_id L=count[7]; // the 7thelement of //count is assigned to L which has been //declared as a reg variable 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  31. 2. Verilog Basic Concepts(11) System Task (1) $display • Syntax: $display(p1, p2, p3, …, pn); $display(“At time %d virtual address is %h”, $time, v_address); // displayed as // At time 200 virtual address is f4 // automatic new-lined after each // $display. Display when it is encountered. 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  32. 2. Verilog Basic Concepts(12) System Task (2) $monitor • Syntax: $monitor(p1, p2, p3, …, pn); $monitor($time, “Values =%b, reset=%b”, clock, reset); // $monitor is activated when any // variable it monitors has just been // changed 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  33. 2. Verilog Basic Concepts(13) System Task (3) $finish • Syntax: $finish; $finish; // complete the simulation. System Task (4) $stop • Syntax: $stop; $stop; // temporally stop the simulation. 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  34. 2. Verilog Basic Concepts(14) • Compilation Directive (1) `define Declaration: `define word_size 32 //define the text macro word_size as 32 Reference: reg [0:word_size-1] counter; //declare counter as a 32 bits reg variable 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  35. 2. Verilog Basic Concepts(15) • Compilation Directive (2) `include Declaration: `include “header.v” // include the file “header.v” 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  36. 3. Gate-level Modeling (1) • Gate Type:and, or, xor, nand, nor, xnor, not module dummy(a,b,c,d,g); input a,b,c,d; a e output g; u1 g b u3 wire e,f; c f and u1(e, a, b); u2 d and u2(f, c, d); or u3(g, e, f); endmodule 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  37. 3. Gate-level Modeling (2) Buf/not Type: buf, not, bufif1, bufif0, notif1, notif0 buf not bufif1 bufif0 notif1 notif0 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  38. 4. Data Processing (1) • Continuous assignment 連續指定 • Type of Delay • Expression, Operand and Operators 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  39. 4. Data Processing (2) • Continuous assignment • Examples: wire sum; assign sum= a^b^cin; // reg sum; //always @ (a or b or cin) // sum=a^b^cin; assign #10 sum= a^b^cin; (for sim) wire #10 sum= a^b^cin; wire #10 sum; assign sum= a^b^cin; 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  40. 4. Data Processing (3) • Operators • Arithmetic: * (unsigned multiply), / (division), + (addition) , - (subtraction) • Logic: ! (not), && (and), ||(or) example: if (a==1’b1 && ~b==1’b0) K=….. ; If (!(~a|b==1’b1)) If ((~a|b!=1’b1)) 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  41. 4. Data Processing (4) • Operators (cont.) • Comparison: > (greater), <(smaller), >=(greater or equal to), <= (smaller than or equal to). • Equality: == (equal to), != (not equal), ===(equal on event), !==(not equal on event), 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  42. 4. Data Processing (5) • Operators (cont.) • Bit-wised Operators: ~ complement & Bit-wised and | Bit-wised or ^ Bit-wised xor ^~ or ~^ Bit-wised xnor Examples: A= 1011 B= 1101 C=~B //C=0010 C=A&B; //C=1001 C=A|B; //C=1111 C=A^B;//C=0110 C=A~^B;//C=1001 逐位元運算 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  43. module ALU (sel, a, b, c, cbout); input [2:0] sel; input [3:0] a, b; output [3:0] c; output cbout; reg [3:0] c; reg cbout; always @(sel or a or b) case (sel) 3’b001: c=~b; 3’b010: c=a&b; ….. xxxx: {cbout, c}=a+b; yyyy: {cbout, c}=a-b; default: ; endcase endmodule

  44. `include “c:/xilinx/ylj/bitwised_op/bitwised_op.v” module test_ALU; reg [4:0] i, j; reg [3:0] k, sel1; reg [3:0] a1, b1; wire [3:0] c1; wire cbout; ALU uut (.sel(sel1), .a(a1), .b(b1), .c(c1), .cbout(cbout)); initial for (i=0; i<=5’d15; i=i+1) begin a1=i; for (j=0; j<=5’d15; j=j+1) begin b1=j; for (k=1; k<=3’d7; k=k+1) begin sel1=k; #5 $display(“a=%d, b=%d, sel=%d, c=%d, cbout=%b”, a1, b1, sel1, c1, cbout); end end end endmodule

  45. 4. Data Processing (6) • Operators (cont.) • Reduction Operators : & Reduction and ~& Reduction nand | Reduction or ~| Reduction nor ^ Reduction xor ~^ or ^~ Reduction xnor 減縮運算 Examples: A = 0110 B=&A; //B=0 B=|A; //B=1 B=^A; //B=0 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  46. 4. Data Processing (7) • Operators (cont.) • Shift operators: >> shift right << shift left Examples: A= B>>4; //B=011010, A=000001 E= D<<2; //D=100101, E=010100 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

  47. 算術移位 • underflow 算術右移 a=0110 (+6) =>a=0011(+3)=>a=0001=> a=0000=> a=0000=> b=1000 (-8) =>b=0100(+4) =>b=1100(-4)=>b=1110(-2)=> b=1111(-1)=> b=1111(-1) 符號擴充 (Sign Extension) 算術左移 a=0001 =>a=0010=>a=0100=>a=1000 (overflow 溢位) b=1110(-2) => b=1100(-4)=> b=1000 (-8) =>b=0000 (overflow) underflow •

  48. module arith_shift (sel, A, B, num, V); input sel; input [4:0] A; input [2:0] num; output [4:0] B; output V; reg [4:0] B; reg V; reg temp; always@(sel or A or num) if (sel==1’b1) begin V=1’b0; case (num) 3’d1: B={A[4], A}>>1; 3’d2: B={A[4], A}>>2; 3’d3: B={A[4], A}>>3; 3’d4: B={A[4], A}>>4; 3’d5:B={A[4], A}>>5; // B=5{A[4]}; default: ; endcase end else // sel==1’b0 begin temp=A[4]; case (num) 3’d1: B=A<<1; ………….. default: ; endcase V=temp ^ B[4]; end endmodule

  49. `include “arith_shift.v” module st_arith_shift; wire [4:0] b; wire v; reg [4:0] a; reg [2:0] num; reg [5:0] i; reg [2:0] j; reg sel; arith_shift u1 (sel, a, b, num, v); initial begin sel=0; repeat(2) begin for (i=1; i<=6‘d31; i=i+1) begin a=i; for (j=1; j<=3’d5; j=j+1) begin num=j; #5 $display ($time, “sel=%b,a=%b, num=%d, b=%b, v=%b”, sel, a, num, b, v); end end sel=~sel; end //repeat $finish; end //initial endmodule

  50. 4. Data Processing (8) • Operators (cont.) • Concatenation operator { } concatenation { { } } repeat Examples: {cout, sum}= a+b+cin; Y={4{A}, 2{B}, C} ; = {A,A,A,A,B,B,C} 九十一學年度國立高雄應用科技大學IC設計研習班 蔣元隆博士撰 92.3.1

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