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Efficient Low-Cost SOC Debug Platform with On-Chip Test Architectures

This study presents a low-cost SOC debug platform utilizing on-chip test architectures. As chip complexity increases, so does the likelihood of bugs, impacting time-to-market. The proposed method leverages JTAG, ICE, run-stop mechanism, and trace features efficiently on a single port in the SoC or NoC, eliminating the need for a separate controller. Experimental results validate the effectiveness of this approach at the SOCC 2009 IEEE International Conference.

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Efficient Low-Cost SOC Debug Platform with On-Chip Test Architectures

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  1. A Low-Cost SOC Debug Platform Based on On-Chip Test ArchitecturesKuen-Jong Lee, Si-Yuan Liang and Alan SuDept. EE, NCKU ; GUC Presenter : Shoa-ChiehHou SOC Conference, 2009. SOCC 2009. IEEE International 

  2. What’s the problem? • Increasing of the chip complexity • Bug also increase • Time to market • JTAG is widely used method • ICE • Run stop mechanism • Trace • Usually one port for JTAG in SoC or NoC • Controller needed

  3. Propose method

  4. Experimental Results

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