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Research and Development of FPGA IV&V Methods

This project aims to develop deployable IV&V methods for FPGA applications, addressing both abstract representations and physical implementations. It involves surveying existing applications, analyzing concept/requirements, implementing dynamic analysis, defining validation methods, and project transference.

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Research and Development of FPGA IV&V Methods

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  1. Research and Development of Deployable IV&V Methods for FPGA ApplicationsNorthrop Grumman, KeyLogic Systems, Mountain State Information Systems, Inc., The University of Montana and West Virginia University July 20, 2006

  2. Project Need • What are the methods/procedures/standards for analysis of FPGAs? • Provide field proven Work Instruction to the IV&V Practitioner • Establish IV&V’s role in the analysis of FPGAs • Develop an overall IV&V strategy and position • Address static and dynamic needs/methods across full life-cycle • FPGAs are playing increasingly prominent roles in NASA missions • They are partially hardware and partially software • They are attractive because they do not have the month(s) lag time associated with manufacturing custom chips but provide many of the same features • FPGA IV&V methods are accurately documented and communicated High speed software functions are evolving to FPGAs in NASA missions. IV&V of these devices is important to the agency to maximize mission success.

  3. What are challenges in FPGA IV&V? • FPGAs straddle: • Abstract representations like SW (HDL) • Physical implementations like Digital Design KHz MHz GHz Some challenges here different than FSW: Timing, Loading, Integrated package (circuit/software) -- requires dynamic IV&V analysis methods Effective FPGA IV&V addresses both the abstract representation and the physical implementation

  4. Approach This is a “standard initiative” with 5 steps: 1. Surveying and cataloging existing FPGA applications 2. Concept/Requirements Phase: • Methods for Concept/Requirements analysis • Identify potential methods for full-lifecycle analysis 3. Design/Implementation Phase: • Dynamic analysis including functional and timing simulations at the unit level • Envisioned work instructions build on successful MRO analysis methods 4. Test Phase: • Define the types of design and implementation validation that can be practically accomplished via subsystem testing 5. Project transference: Continue with pilot and other projects Steps 1-4 occur in Year 1, and Step 5 in Year 2

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