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Uses of Synchronized Clocks in Test and Measurement Systems

Learn how IEEE 1588 protocol is used to synchronize real-time clocks in distributed systems for test and measurement applications. Explore synchronization basics, timing support, clock control, and infrastructure, along with applications in various industries. Discover how to achieve sub-nanosecond accuracy and the benefits of using LXI Class A and B instruments for precise measurements.

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Uses of Synchronized Clocks in Test and Measurement Systems

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  1. Uses of Synchronized Clocks in Test and Measurement Systems Jeff Burch, Adam Cataldo, John Eidson, Andrew Fernandez, Conrad Proft, Dieter Vook Measurement Research Laboratory, Agilent Technologies, Inc. CHESS

  2. Agenda • Overview of clock synchronization and driving applications • Test & measurement (LXI Class B instrumentation & DAQ) • Experimental results • Conclusions CHESS

  3. Purpose of IEEE 1588 IEEE 1588 is a protocol designed to synchronize real-time clocks in the nodes of a distributed system that communicate using a network It does not say how to use these clocks (this is specified by the respective application areas) CHESS

  4. Coupling IEEE 1588 to your application CHESS

  5. Synchronization Basics – Delay Request-Response Mechanism CHESS

  6. Under the assumption that the link is symmetric Offset = (Slave time) – (Master time) = [(t2 – t1) – (t4 – t3)]/2 = [(t-ms) – (t-sm)]/2 (propagation time) = [(t2 – t1) + (t4 – t3)]/2 = [(t-ms) + (t-sm)]/2 Can rewrite the offset as Offset = t2 – t1 – (propagation time) = (t-ms) – (propagation time) If the link is not symmetric The propagation time computed as above is the mean of the master-to-slave and slave-to- master propagation times The offset is in error by the difference between the actual master-to-slave and mean propagation times Synchronization Basics – Delay Request-Response Mechanism - 2 CHESS

  7. Synchronization Basics – Peer Delay Mechanism CHESS

  8. Application IEEE 1588 Timing Support (e.g. time stamping, time triggers…) Application Code IEEE 1588 Clock IEEE 1588 IEEE 1588 Code Control OS MAC MII IEEE 1588 Packet Detection PHY LAN IEEE 1588 CHESS

  9. The residence time is accumulated in a field of the Sync (one-step clock) or Follow_Up (two-step clock) messages End-to-End Transparent Clocks CHESS

  10. How well can you synchronize? From: “DP83640 Synchronous Ethernet Mode: Achieving Sub-nanosecond Accuracy in PTP Applications, National Semiconductor Application Note 1730, David Miller, September 2007 CHESS

  11. Infrastructure: Boundary and transparent clocks (IEEE 1588 bridges): Hirschmann, Westermo, Cisco, others GPS master clocks: Symmetricom, Meinberg, Westermo,… Silicon: Microprocessors with embedded 1588: Intel, Hyperstone, Freescale, AMCC,… PHY/MAC level: National Semiconductor, others in proto or 1st silicon (some also implement synchronous Ethernet) Protocol & misc: 1588 stacks, IP blocks, consulting: IXXAT,U. Zurich, MoreThanIP, others Wireshark Products (partial listing) CHESS

  12. Websites General IEEE 1588 site: contains product pointers, conference records, general guidance, standards related http://ieee1588.nist.gov/ ISPCS (International IEEE Symposium on Precision Clock Synchronization) site: Conference on IEEE 1588 and related subjects http://www.ispcs.org/ CHESS

  13. RoboTeam in Action: Process Relative Motion Courtesy of Kuka Robotics Corp. CHESS

  14. e.g. high speed printing Courtesy of Bosch-Rexroth. CHESS

  15. IEEE 1588 enabled flight test instrumentation in the forward fuselage of a test aircraft. (Data acquisition) Courtesy of Teletronics CHESS

  16. GE uses 1588 in the Mark™ Vie control system for large generators, turbines, wind farms, and other DCS applications. (>50K I/O Packs with 1588 shipped to date) http://gepower.com/prod_serv/products/oc/en/control_solution/ppc_markviedcs_cs.htm Power System Applications (Courtesy of General Electric) CHESS

  17. IEEE Power System Relaying Committee (PSRC) recently approved formation of Working Group H7  "IEEE 1588 Profile for Protection Applications" Power System Applications CHESS

  18. Cellular backhaul is the major telecom application to date. Metro-Ethernet in field trial. Femtocells beginning. Companies involved (partial list): Nokia-Siemens, Brilliant, Semtech, Zarlink, … Telecommunications Applications CHESS

  19. Consumer electronics: IEEE 802.1as http://www.ieee802.org/1/pages/802.1as.html The “AVB” effort should be carefully investigated by both PTIDES and PRET. Audio/video systems applications CHESS

  20. LXI Class A Instrument TX RX 8 LVDS Trigger Bus • LXI Class A • Trigger Bus LXI Class A&B Instrument Overview LXI Class-C Instrument LXI Class B Instrument Meas FW Meas HW DUT HTTP LAN TCP PHY SCPI UDP TT TS P2P App Code Event Log IEEE1588 • LXI Class B • IEEE1588 Clock Sync • Peer-to-Peer Messages • Event Logs • Downloaded Application Code CHESS

  21. LXI Class A&B benefits • Class B: • Increased visibility of system configuration, timing and performance • Increased visibility for fault diagnosis and trouble shooting • Ability to precisely time measurement execution and state evolution system-wide • Increased ability to optimize system performance, e.g. throughput, timing precision • Increased ability to do cross domain measurement correlations based on precisely time stamped data • Class A: • Increased traditional triggering flexibility: 8-wide, daisy chain CHESS

  22. DEMO TIME! CHESS

  23. LXI Class B experimental test system • Experiments: • Frequency response • Fault shutdown Test system block diagram CHESS

  24. LXI Class B experimental test system CHESS

  25. PC Paced Instrument Sequencing-frequency response *TRG; *OPC? HW Trigger DONE *TRG; *OPC? HW Trigger DONE CHESS

  26. Instrument Sequencing by PC (Baseline) Irregular signal timing due to timing jitter in PC CHESS

  27. Peer-to-Peer Instrument Sequencing MEASURE STEP MEASURE STEP COMPLETE CHESS

  28. Instrument Sequencing by P2P Messages More regular signal timing CHESS

  29. TT TT TT TT TT TT TT TT LXI Class B: Time-Triggered Instrument Sequencing Time overlap COMPLETE CHESS

  30. Instrument Sequencing by Time-Triggers Shorter interval due to overlap CHESS

  31. Sequencing to measure frequency response CHESS

  32. Power Supply Shutdown POLL PC Polled FAULT SHUTDOWN FAULT TS P2P Immediate SHUTDOWN SHUTDOWN FAULT TS P2P Timed TT = TS + Δ1 TT = TS + Δ2 SHUTDOWN SHUTDOWN CHESS

  33. PC polled Asynchronous Fault TT-Fault FET 1. Short PS load 2. PS shuts off 3. Turn off FG 4. Turn off DMM Protect PS-Volt Shutdown FG-out DMM-off Shutdown CHESS

  34. Time-Triggered Emergency Shutdown Asynchronous Fault Protect Shutdown Δ1 Shutdown Δ2 CHESS

  35. Power Shutdown performance CHESS

  36. Power Shutdown Event Log-based Analysis PS FGEN DMM Common Time Scale CHESS

  37. Conclusions: • Benefits of Class A & B: • Increased visibility of system configuration, timing and performance • Increased visibility for fault diagnosis and trouble shooting • Ability to precisely time measurement execution and state evolution system-wide • Increased ability to optimize system performance, e.g. throughput, timing precision • Increased ability to do cross domain measurement correlations based on precisely time stamped data • Increased traditional triggering flexibility: 8-wide, daisy chain Performance measurements illustrate these benefits. CHESS

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