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Verification Environment for PixelChip Readout System

This document outlines the current status of the PixelChip harness verification environment as of January 29, 2014. It includes a block diagram detailing components such as the top test library, environment analysis, trigger logic, and readout verification. The Pixel Region (PR) buffer is characterized as an array of queues managing Time of Arrival (ToA) and Time over Threshold (ToT) data. We discuss the issues faced with the PR buffer, monitoring requirements, and propose a temporary workaround for ToA equalization in readout transactions, aiming to ensure efficient data processing and integrity.

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Verification Environment for PixelChip Readout System

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  1. VEPIX53: Current status Elia Conti 29/01/2014

  2. Block diagram of the verification environment • top test lib • top base test • top test1,2… top env analysisenv hit env readoutenv trigger env top virtualsequencer PixelChipHarness Clock and resetgenerator PixelChip DUT hit_if analysis_if trig_if readout_if PixelChipInterfaces

  3. DUT Pixel Chip • PR buffer is an array of queues • Each queue stores ToA + ToT from each pixel Pixel Region (PR) PR buffer Pixel matrix ToA HITS HIT PACKETS ToT ToT conv. Digital PUC PixelChipHarness TRIGGERLOGIC ..... ..... ..... TRIGGER TIME TAG END OF COLUMN (externalToAcounter) PIXEL BUSY FLAGS PR BUFFER FULL FLAG

  4. Readout verification component (I) • readout_monitor collects PR buffer output and builds readout_trans transactions • PR buffer does not work as desired because each output is updated every time a nonzero packet is selected by trigger • Persistence of past output in readout_trans: readoutenv readout master agent readout monitor

  5. Readout verification component (II) readoutenv readout master agent readout monitor • Temporary workaround:ToAequalization of readout_trans transactionsin readout_monitor

  6. New version of PR buffer • State machine diagram reset = 0 ToA < timeTag- latency ToA > timeTag - latency dout = 0 IDLE ToA == timeTag - latency wr_en = 1 MATCH WRITE ToA == timeTag - latency fifo.push_front(packet) dout = fifo.pop_back()

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