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Team M1 Enigma Machine Milestone 7 - 26 March, 2006

Team M1 Enigma Machine Milestone 7 - 26 March, 2006. Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka. Design Manager: Prateek Goenka. Status. STATUS. Finished: Behavioral Verilog and C simulation Structural Verilog Logic optimization

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Team M1 Enigma Machine Milestone 7 - 26 March, 2006

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  1. Team M1Enigma MachineMilestone 7 - 26 March, 2006 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka Design Manager: Prateek Goenka

  2. Status STATUS • Finished: • Behavioral Verilog and C simulation • Structural Verilog • Logic optimization • Module-level spice delay and power simulations • Floorplan • Top-level schematic testing • In Progress: • Functional block layout • Simulation of functional blocks • To do: • Global Layout • Testing • Simulation

  3. Design Decisions • Finalized the SRAM design • Layout of Add_Mod26 • Layout of 3-bit and 5-bit counter cells • Updated layout of Wheel Counter • Floorplan

  4. Initial Floorplan

  5. UPDATED FLOORPLAN

  6. Register Schematic Delay: 68ps ExtractedRC Delay: 94ps

  7. Schematic of Add_Mod26

  8. LAYOUT OF ADD_MOD26

  9. LOOKAHEAD MODULE LAYOUT

  10. LOOKAHEAD2 MODULE LAYOUT

  11. SUBTRACTOR MODULE LAYOUT

  12. 3-bit Comparator

  13. 3-bit Counter Cell 3, 1-bit T Flips Flops Count Logic

  14. 3-bit Counter

  15. 5-bit Counter Cell Count Logic w/ Reset at 26 5, 1-bit D/T Flips Flops

  16. Wheel Counter Plan (Module layout and wire planning) 5-bit Counter Cell Wheel Select Data from counters 5-bit Counter Cell Wheel Position

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