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Design of a 7-bit 1GSPS Folding-Interpolation A/D Converter with Self-Calibration Technique

This paper presents the design of a high-speed 7-bit Analog-to-Digital Converter (ADC) capable of 1 GSPS (giga samples per second) using a Folding-Interpolation (F/I) architecture. The focus is on achieving low power consumption, minimal chip area, and high-speed conversion rates. A novel self-calibration technique is introduced to reduce offset errors, enhancing the accuracy and reliability of the ADC's performance. The paper details the circuit design, measurement results, and final conclusions drawn from the implemented system, demonstrating its effectiveness.

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Design of a 7-bit 1GSPS Folding-Interpolation A/D Converter with Self-Calibration Technique

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  1. <ICECS 2010> Design of a 7-bit 1GSPS Folding-Interpolation A/D Converter with Self-Calibration Technique Younghoon Kim, Joongwon Jun, Kyuik Cho, Daeyun Kim, Joonho Moon and Minkyu Song Department of Semiconductor Science, Dongguk University

  2. CONTENTS • Motivation • Structure of ADC • Circuit Design • Measurement • Conclusion

  3. I. Motivation

  4. II. StructureofADC • (7bit) High speed ADC main Structure • F/I Structure : Low Power Consumption, Small Chip Area, and High Speed Conversion Rate

  5. III. CircuitDesign ※ The propose design techniques ※ I. F/I structure for low power consumption and small chip area. II. The proposed Self-calibration Circuit.

  6. III. CircuitDesign

  7. III. Circuit Design We need a self-calibration for reduce offset error

  8. III. CircuitDesign

  9. III. CircuitDesign

  10. III. CircuitDesign LSB : 1.7mV It can decide C-DAC resolution for self-calibration

  11. III. CircuitDesign

  12. IV. Measurement

  13. IV. Measurement

  14. IV. Measurement

  15. IV. Measurement

  16. IV. Measurement

  17. V. Conclusion

  18. V. Conclusion

  19. FOM Comparison of 6,7 and 8b ADC

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