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Reiner Hartenstein * Kaiserslautern University of Technology (TU Kaiserslautern)

November 22, 2002, ENE, UnB, Brasilia. Data-stream-based Computing, Enabling Technology for Reconfigurable Computing Friday, November 22, 2002, 17.00 hrs. Reiner Hartenstein * Kaiserslautern University of Technology (TU Kaiserslautern). *) IEEE fellow. >> Microelectronics History.

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Reiner Hartenstein * Kaiserslautern University of Technology (TU Kaiserslautern)

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  1. November 22, 2002, ENE, UnB, Brasilia Data-stream-based Computing,Enabling Technology for Reconfigurable ComputingFriday, November 22, 2002, 17.00 hrs. Reiner Hartenstein* Kaiserslautern University of Technology (TU Kaiserslautern) *) IEEE fellow

  2. >> Microelectronics History • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http://www.uni-kl.de 2

  3. “Mainstream Silicon Application is switching every 10 Years” Makimoto’s Wave “The Programmable System-on-a-Chip is the next wave“ standard µproc., memory 2007 1967 1987 morphware LSI, MSI 1957 ASICs, accel’s 1977 1997 custom Published in 1989 The History of Paradigm Shifts 2ndDesignCrisis 1stDesignCrisis TTL 3

  4. Repeat Success Story by new Machine Paradigm ! Software Industry’s Secret of Success standard µproc., memory TTL 2007 1967 1987 LSI, MSI reconfigurable 1957 ASICs, accel’s 1977 1997 custom The Impact of Makimoto’s Paradigm Shifts Dr. Makimoto: FPL 2000 keynote Procedural personalization via RAM-based Machine Paradigm structural personalization: RAM-based before run time Personalization (CAD) before fabrication 4

  5. Makimoto’s 3rd wave EDA industry paradigm switching every 7 years [Hartenstein] 1999 (Co-) Compilation: data-stream-based DPAs [Keutzer / Newton] McKinsey Curves 1992 Synthesis (HDLs): Cadence, Synopsys ... 1985 Schematics entry: Daisy, Mentor, Valid ... 1978 Transistor entry: Applicon, Calma, CV ... The next EDA Industry Revolution “The Programmable System-on-a-Chip is the next wave“ Von Neumann does not support Morphware: 5

  6. Ubiquitous embedded systems Embedded systems means: • hardware/ software co-design • configware / software co-design • hardware / configware/ software co-design 20 billion µprocessors (2001) > 90% in embedded systems 10 times more programmers will write embedded applications than computer software by 2010 That’s where our graduates will go 6

  7. partitioning Software & Hardw/Configw Embedded Systems Requirement:Hardware/Configware and Software as Alternatives Algorithm Hardw/Configw only Software only Hardware, Configware Software 7

  8. >> fine grain and coarse grain Morphware • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http://www.uni-kl.de 8

  9. no. of masks cost / mio § 12 12 16 20 26 28 30 >30 4 Xilinx Lattice 42% 15% Actel NRE and mask cost [dataquest] . 6% 3 Altera total: $3.7 Bio 37% Top 4 PLD Manufacturers 2000 2 1 mask set cost [eASIC] feature size 0.8 0.6 0.35 0.25 0.18 0.15 0.13 0.1 0.07 Top 4 FPGA Manufacturers 2000 • [Dataquest] > $7 billion by 2003. • FPGAs going into every type of application – also SoC • fastest growing segment of semiconductor market You do not neet specific silicon ! 9

  10. Configware and EDA as the Key Enabler • Growing no. of independent configware houses (soft IP core vendors) and design services provide libraries of "pre-fabricated" re-usable IP cores • Emerging separate EDA software market -FPGA synthesis [2001: Dataquest]: • Synplicity 57%, • Mentor 37%, • Synopsys 7% 10

  11. *) R. Hartenstein: ISIS 1997 L L L S S area used by application hardwired rDPAs (reconfigurable computing)* L L L 2 1 0.5 0.25 0.13 0.1 0,07 DSP FPGAs (reconfigurable logic) 1 Bit CLB S S instruction set processors standard microprocessor Wiring by abutment: 32 Bit example resources needed for reconfigurability L L L Throughput vs. Efficiency T. Claasen et al.: ISSCC 1999 MOPS / mW 1000 100 10 1 0.1 0.01 0.001 µ feature size 11

  12. XPU family (IP cores): PACT AG., Munich http://pactcorp.com Commercial rDPAs ACM: Quicksilver Tech XPU128 12

  13. data streams SNN filter KressArray Mapping Example http://kressarray.de rout thru only array size: 10 x 16 = 160 rDPUs not used backbus connect 13

  14. Select mode, number, width of NNports Select Function Repertory 16 8 32 rout-through only rout-through and function + 24 2 rDPU more NNports: rich Rout Resources select Nearest Neighbour (NN) Interconnect: an example 4 Examples of 2nd Level Interconnect: layouted over rDPU cell - no separate routing areas ! KressArray Family generic Fabrics: a few examples http://kressarray.de 14

  15. Antimatter of Computing is available • Using FPGAs (fine grain morphware) has been just Logic Synthesis on a strange platform • Coarse Grain rDPAs (Reconfigurable Computing): a fundamental Paradigm Shift • up several abstraction levels • Data-stream-based Computing 15

  16. >> Anti Matter of Computing • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http://www.uni-kl.de 16

  17. The anti universe • Paul Dirac predicted a complete anti universe consisting of antimatter • “There are regions in the universe, which consist of antimatter ..... • .... But there are asymmetries” • when a particle hits its antiparticle, both are converted into energy: Annihilation • We are not aware, that there is a new area in computing sciences , which consists of antimatter of computing • Reconfigurable Computing is made from this antimatter: data-stream-based computing 17

  18. hydrogen anti hydrogen • 1954: new accelerators: cyclotron, like Berkeley‘s Bevatron • 1955 Owen Chamberlain et al. create anti proton on Bevatron • 1995: hydrogen anti atom created at CERN – by forcing positron and anti proton to merge by very low energy. anti particles • 1928: Paul Dirac: „there should be an anti electron having positive charge“ (Nobel price 1933) • 1932: Carl David Anderson detected this „positron“ in cosmic radiation (Nobel price 1936) • 1956: anti neutron created on Bevatron • 1965: creation of a deuterium anti nucleus at CERN 18

  19. AntiMatter - + + - machine paradigm: Anti Atom Electron spinning - - The World of Matter - + machine paradigm: the Atom Positron spinning Matter & Antimatter: Atom and Anti Atom 19

  20. AntiMachine paradigm CPU 1936 1st electronic computer (Konrad Zuse) 1946 v. N. machine paradigm data stream spinning instruction stream spinning 1990 anti machine paradigm published 1995 rDPA / DPSS (supersystolic: Rainer Kress) - DPU + - Machine paradigm: „von Neumann“ novel compilation techniques + Matter & Antimatter of Informatics : Machine and Anti Machine 1971 1st microprocessor (Ted Hoff) 1979 „data streams“ (systolic array: Kung / Leiserson) all ingredients available 20

  21. CPU Data Path + + + + + instruction sequencer - DPU DPU DPU + - data streams data stream Data Path Unit Data Path Unit instruction stream Matter vs. antimatter: CPU vs. DPU there are asymmetries 21

  22. - DPU DPU DPU DPU DPU DPU DPU DPU DPU - - - - - - - - - - DPA + + + + + + + + + coherent data streams spinning around DPA heavy anti atoms: DPA = DPU array 22

  23. + + + + + + + - - - - - - - Parallelism by Concurrency independent instruction streams difficult ... 23

  24. >> Anti Machine and its Resources • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http://www.uni-kl.de 24

  25. asM M asM M instruction stream data streams (r) DPU data stream (r)DPU CPU or DPU M M M M M M M M (r)DPA (r)DPU Array address generator instruction sequencer Dichotomy of machine paradigms there are asymmetries 25

  26. DPA r DPU r instruction sequencer DPU DPU CPU Terminology: DPU versus CPU ... • DPU: data path unit • DPA: DPU array • GA: gate array • rDPU: reconfigurable DPU • rDPA: reconfigurable DPA • rGA: reconfigurable GA • DPU is no CPU: there is nothing central - like in a DPA 26

  27. Terminology: Digital System Platforms clearly distinguished 27

  28. time input data streams DPA x x x x ... which data item at which time at which port x x x x time port # | x | | time - - - x x x - - - - x x x x x x x x x - - - - - x x x - | | | x x x - - | | | port # | | | port # x | | | x x | | x x x output data streams x x x time flowware defines .... flowware manipulates the data counter(s) ... ... software manipulates the program counter 28

  29. high level source program asM wrapper data streams intermediate M M M M mapper rDPA M M configware scheduler r. Data Path Array M M M M M M M M M M flowware address generator Configware / Flowware Compilation data sequencer 29

  30. “instructions” rDPA Compiler Memory (data memory) Scheduler memory bank memory bank memory bank ... memory bank ... Sequencers (data stream generator) memory bank ... for a Stream-based Soft Machine 30

  31. goto PixMap[1,1] HalfZigZag; SouthWestScan uturn (HalfZigZag) x EastScan is step by [1,0] end EastScan; y SouthScan is step by [0,1] endSouthScan; NorthEastScan is loop8 times until [*,1] step by [1,-1] endloop end NorthEastScan; HalfZigZag HalfZigZag data counter data counter HalfZigZag is EastScan loop 3 times SouthWestScan SouthScan NorthEastScan EastScan endloop end HalfZigZag; data counter data counter *> Declarations JPEG zigzag scan pattern Flowware language example (MoPL) SouthWestScan is loop8 times until [1,*] step by [-1,1] endloop end SouthWestScan; The same language principles 31

  32. ceiling floor sliders B B 0 0 D D A A [ L L 0 0 ] B B L L 0 0 0 0 [ ] GAG Slider Model GAG Generic Address Generator 32

  33. floor ceiling slider B F 0 floor slider GAG Slider Operation Demo Example address 33

  34. GAG GAG DA DA DA L0 L0 L0 B0 B0 B0 VLIW stack GAU Address Stepper Address Stepper Address Stepper Base Slider Base Slider Base Slider Limit Slider Limit Slider Limit Slider GAU GAG GAG A A A SDS GAU GAG Complex Sequencer Implementation all `been published in 1990 Generic Addressing Unit 34

  35. DA L0 B0 Address Stepper Base Slider Limit Slider a) b) GAU A c) until d) e) f) g) Generic Sequence Examples atomic scan linear scan video scan -90º rotated video scan -45º rotated (mirx (v scan)) sheared video scan non-rectangular video scan zigzag video scan spiral scan feed-back-driven scans perfect shuffle published in 1990 35

  36. w/r r r Bank a r r r Bank b final design Bank a r r r after inner scan line loop unrolling after scan line unrolling hardw. level access optim. initial design Storage scheme optimization: scanline unrolling MoM anti machine architecture 36

  37. >> Problems to be solved • Microelectronics History • fine grain and coarse grain Morphware • Anti Matter of Computing • Anti Machine and its Resources • Problems to be solved http://www.uni-kl.de 37

  38. What is the trend ? • Data-stream-based Computing is heading for mainstream • 1979 „data streams“ (Kung / Leiserson) • 1997 SCCC (LANL) Streams-C Configurabble Computing • SCORE (UCB) Stream Computations Organized for Reconfigurable Execution • ASPRC (UCB) Adapting Software Pipelining for Reconfigurable Computing • 2000 Bee (UCB), ... • Most stream-based multimedia systems, etc. • Many other areas .... • vN is needed for embedded systems, OS, compilers, Sauerkraut software, non-performance-critical applications, others …. • vN is obsolete for massive parallelism, except some special application areas • Anti machine is the way to go for massive parallelism, also data-intensive applications • Morphware is the way for high performance with short product life cycles, unstable standards 38

  39. courses / embedded tutorials: • DATE. Munich, 2001 • ASP-DAC, Yokohama, 2001 • SBCCI, Brasilia, 2001 • languages full day courses: Univ. Montpellier 1998 Nokia / Univ. Tampere, Finland, 2002 CNRS Paris France, 2002 UnB, Brasilia, 2002 • hw / sw partitioning methodology • compilation techniques • 10 keynotes 2001 / 2002 • 5 invited talks 2001 / 2002 • anti architectural resources • sequencing methodology: hw & sw Conclusion: all knowledge needed is available • machine paradigm • parallel memory IP core and module generator vendors • anything else needed 39

  40. this dichotomy is completely ignored by our CS curricula computing computing systolic in space in time arrays etc. migration by re-timing and other transformations Main problems to be solved • Lack of qualified users and implementers • Each programmer should have qualified awareness on dichotomy and morphware • curricular innovations are urgently needed 40

  41. procedural structural Annihilation? software person hardware person CS education ..... Configware / Software Co-Design? Hardware / Software Co-Design? 41

  42. - - + crash + + - Annihilation? avoidable by careful methodology 42

  43. … is based on the Submarine Model Algorithm Software procedural high level Programming Language Brain usage: procedural-only Assembly Language Hardware invisible: under the surface Hardware However, current CS Education …. This model disables ... Software Faculty Colleagues shy away from the Paradigm Shift: 43 their Brain hurts? - can’t be: this Half has been amputated

  44. procedural structural partitioning Brain Usage: both Hemispheres Hardware and Software as Alternatives Algorithm Hardw/Configw only Software only Software & Hardw/Configw Hardware, Configware Software 44

  45. Hardware (procedural) structurally disabled … completely disabled to cope with solutions other than software only The Dominance of the Submarine Model ... ... indicates, that our CS education system produces zillions of mentally disabled Persons It‘s time to attack the software faculty dictatorship. Get involved! 45

  46. Antimatter Search Antimatter Search ? in EE & CS we do not need to search 46

  47. >>> thank you thank you for your patience 47

  48. >>> END END 48

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