'25 mbyte' diaporamas de présentation

GENERAL

GENERAL. Inspired by LeCroy ULM Originally designed for MSU specs 72 ECL Ports XCS40XL FPGA TMS320C6711 floating point DSP (900 Mflops/s) 2 banks of fast asynchronous SRAM 2-Mbytes/ea VMEbus interface Internal clock rate 80 MHz 25 Mbyte/s actual transfer rate. Interface. FPGA.

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