40 mhz clock - PowerPoint PPT Presentation

L0 processor for NA62

L0 processor for NA62. Marian Krivda 1) , Cristina Lazzeroni 1) , Roman Lietava 1)2) 1) University of Birmingham, UK 2) Comenius University, Bratislava, Slovakia. Content. Requirements Block diagram Board layout and front panel Trigger message from each sub-detector

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Richard Kass

Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector. K.E. Arms, K.K. Gan, M. Johnson, H. Kagan, R. Kass, C. Rush, S. Smith, R. Ter-Antonian, M.M. Zoeller The Ohio State University A. Ciliox, M. Holder, M. Ziolkowski Universitaet Siegen, Germany. Richard Kass.

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183 views • 16 slides

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