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Implementing a Functional/Timing Partitioned Microprocessor Simulator with an FPGA

HASim. Nirav Dave*, Michael Pellauer*, Joel Emer † *, &amp; Arvind* Massachusetts Institute of Technology* Computer Science and Artificial Intelligence Lab Cambridge, MA Intel Corporation VSSAD † Hudson, MA. Implementing a Functional/Timing Partitioned Microprocessor Simulator with an FPGA.

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林仲祥 , 李苡嬋 CSIE, NTU 11 / 03, 2008

ACA2008 HW3. Simplescalar: Victim Cache. 林仲祥 , 李苡嬋 CSIE, NTU 11 / 03, 2008. ISCA’90 (Norman P. Jouppi) “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers”. Victim Cache. 2. Victim Cache. General cache. data. Data. Hit.

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186 views • 14 slides

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