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MIPS processor continued

MIPS processor continued. Jump Instruction. Jump instruction seems easy to implement We just need to replace the lower 28 bits of the PC with the lower 26 bits of the instruction shifted by 2 bits The shift is achieved by simply concatenating 00 to the jump offset. 31. 26. 25. 0. 0. 0.

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MIPS processor continued

MIPS processor continued. In Class Exercise Question. Show the datapath of a processor that supports only R-type and jr reg instructions. In Class Exercise Answer. Show the datapath of a processor that supports only R-type and jr reg instructions. 0MUX1. 25:21. 20:16. 15:11. Performance.

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MIPS processor continued

MIPS processor continued. Performance. Assume that Memory access: 200ps ALU and adders: 100 ps Register file read: 50ps Register file write: 10ps (the clk-to-q delay) PC update: 10ps (the clk-to-q delay) The setup time of DFFs: 10ps Other parts do not have delay How fast is

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MIPS processor continued

MIPS processor continued

MIPS processor continued