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Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers

Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers. Manu Awasthi , David Nellans , Kshitij Sudan, Rajeev Balasubramonian, Al Davis University of Utah. Takeaway. Multiple, on-chip MCs will be common in future CMPs, with multiple cores sharing one MC

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390 views • 28 slides

Mrinmoy Ghosh Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Tech

Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. Mrinmoy Ghosh Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Tech . Motivation. Increase in DRAM power consumption Increasing DRAM density

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384 views • 24 slides

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Dram energy - PowerPoint PPT Presentation

Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers

Mrinmoy Ghosh Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Tech