'Dual rail' diaporamas de présentation

Elastic circuits

1.17k views • 93 slides

Bridging the gap between asynchronous design and designers

623 views • 52 slides

Design of an Asynchronous Reconfigurable Cell for Conformal Computing

Design of an Asynchronous Reconfigurable Cell for Conformal Computing. Mariam Hoseini. Advisor: Dr. Chao You Supervisor: Dr. Mark Pavicic Committee members: Dr. Rajendra Katti, Dr. Subbaraya Yuvarajan, Dr. Deying Li. North Dakota State University April 2009. Agenda.

504 views • 42 slides

Practical Design and Performance Evaluation of Completion Detection Circuits

Practical Design and Performance Evaluation of Completion Detection Circuits. Fu-Chiung Cheng Department of Computer Science Columbia University. Reading 4. Outline. Motivation Previous Work New Completion Detection Circuit Performance Evaluation Conclusion. Motivation.

556 views • 41 slides

Bridging the gap between asynchronous design and designers

Bridging the gap between asynchronous design and designers. Hao Zheng. Outline. What is an asynchronous circuit ? Asynchronous communication Asynchronous design styles (Micropipelines) Asynchronous logic building blocks Control specification and implementation

606 views • 38 slides

Randy J. Chen July 1, 2013

Randy J. Chen July 1, 2013. Cyclic Node Merging Outline. Motivation Problem Formulation Cyclifiable Structure Identification Cyclic Substitute Node (CSN) Added Cyclic Substitute Node (ACSN) Cyclifiable Structure Validation Intra-SCC Validation Inter-SCC Validation Proposed Flow

507 views • 38 slides

Student: Jui -Hung Chen Advisor: Chun-Yao Wang July 18, 2013

Making Combinational Circuits Cyclifiable. Student: Jui -Hung Chen Advisor: Chun-Yao Wang July 18, 2013. Making Combinational Circuit Cyclifiable Outline. Motivation Problem Formulation Cyclifiable Structure Identification & Creation Cyclic Substitute Node (CSN)

495 views • 36 slides

High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths

High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths. Montek Singh and Steven Nowick Columbia University New York, USA {montek,nowick}@cs.columbia.edu http://www.cs.columbia.edu/~montek.

488 views • 35 slides

424 views • 34 slides

Clockless Logic or How do I make hardware fast, power-efficient, less noisy, and easy-to-design?

Clockless Logic or How do I make hardware fast, power-efficient, less noisy, and easy-to-design?. Montek Singh Tue, Jan 14, 2003. Course Information (1). Course Number: COMP290-084 Time and Place Tue/Thu 3:30-4:45pm, Sitterson Hall 325 Instructor Montek Singh

431 views • 31 slides

Emerging Technologies of Computation

Emerging Technologies of Computation. Montek Singh COMP790-084 Oct 27, 2011. Today: Basics of Asynchronous Design. Introduction to Asynchronous Design What is asynchronous design? Why do we want to do it? Data Representation and Communication

436 views • 31 slides

Dual-Rail Control Logic for Enhanced Circuit Robustness

Andrey Mokhov, Victor Khomenko Danil Sokolov, Alex Yakovlev. Dual-Rail Control Logic for Enhanced Circuit Robustness. Motivation. Optimal operating voltage lies near or below sub-threshold voltage Low voltage leads to u npredictable delay variations

339 views • 21 slides

Dual-Rail Control Logic for Enhanced Circuit Robustness

Andrey Mokhov, Victor Khomenko Danil Sokolov, Alex Yakovlev. Dual-Rail Control Logic for Enhanced Circuit Robustness. Motivation. Optimal operating voltage lies near or below sub-threshold voltage Low voltage leads to u npredictable delay variations

217 views • 21 slides

Appro Products and Solutions

Appro Products and Solutions. Appro , Premier Provider of Scalable Supercomputing Solutions: 9/1/09. Anthony Kenisky, Vice President of Sales. Company Overview. :: Appro at a glance. Leading developer of high performance servers, clusters and supercomputer Solutions Established in 1991

315 views • 17 slides

Priority Arbiters

Priority Arbiters. Alex Bystrov David Kinniment Alex Yakovlev. University of Newcastle upon Tyne, UK. Outline of presentation. Need for different arbitration disciplines Types of arbiter A static priority arbiter A dynamic priority arbiter Speed improvements Results Conclusions.

255 views • 16 slides

Clockless Computing

213 views • 14 slides

Bundled-Data Datapaths

Bundled-Data Datapaths. Problems random standard cell layout mixed control + datapath timing analysis required robustness of design reduced Possible Solutions DI codes hybrid bundled + DI simpler timing analysis. DI Codes. Dual Rail (used in 1st Tangram system)

145 views • 14 slides

Building Asynchronous Circuits With JBits

Building Asynchronous Circuits With JBits. Eric Keller eric.keller@xilinx.com FPL 2001. FPL2001. JBits Background. A Java API to configure Xilinx FPGA bitstreams Provides complete design control Routing CLB configuration Supports run-time reconfiguration

230 views • 13 slides

Low Power Design for Wireless Sensor Networks

Low Power Design for Wireless Sensor Networks. Aki Happonen. Table of Contents. Introduction Digital Design RF Design Conclusions. Many cases wireless sensors are deployed to remote location without capability to replace battery.

322 views • 11 slides

Low Power Design for Wireless Sensor Networks

Low Power Design for Wireless Sensor Networks. Aki Happonen. Table of Contents. Introduction Digital Design RF Design Conclusions. Many cases wireless sensors are deployed to remote location without capability to replace battery.

117 views • 11 slides