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Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set

Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set. Tezaswi Raja, Rutgers University Tezaswi@caip.rutgers.edu Vishwani D. Agrawal, Agere Systems va@agere.com http://cm.bell-labs.com/cm/cs/who/va Michael L. Bushnell, Rutgers University

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362 views • 28 slides

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. Tezaswi Raja Vishwani Agrawal Michael L. Bushnell Rutgers University, Dept. of ECE Piscataway, NJ 08854 Support from National Science Foundation, USA. Power in a CMOS Gate. VDD = 5V. IDD. Ground.

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272 views • 26 slides

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Minimum Dynamic Power Design of CMOS Circuits by Linear Program Using Reduced Constraint Set

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program