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Low-capacitance CCD

Low-capacitance CCD . Chris Damerell (R.A.L.), Brian Hawes (Oxford Univ) An idea to reduce the inter-gate capacitance in CPCCDs, hoping to achieve busline distribution of clocks. Present designs load as much as 40nF on the Clock Input lines, and require 20-Amps at 50Mhz. Not easy to provide.

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Low-capacitance CCD