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Lecture 21 I DDQ Current Testing

Lecture 21 I DDQ Current Testing. Definition Faults detected by I DDQ tests Vector generation for I DDQ tests Full-scan Quietest Instrumentation difficulties Sematech study Limitations of I DDQ testing Summary. Motivation.

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IDDQ Testing

New Graphical I DDQ Signatures Reduce Defect Level and Yield Loss ( U. S. Patent Pending) Lan Rao Michael L. Bushnell Vishwani Agrawal ECE Dept., Rutgers U., Piscataway, NJ. IDDQ Testing. VDD = 5V. IDD. IDDQ fault. Ground. Ref. Chakravarty and Thadikaran, 1997.

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972 views • 16 slides

EE 587 SoC Design & Test

EE 587 SoC Design & Test. Partha Pande School of EECS Washington State University pande@eecs.wsu.edu. Midterm Review. Wire Characteristics. Wire modeling in details Wire delay and buffer insertion Uniform and non uniform buffer insertion How scaling changes characteristics of a chip.

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278 views • 15 slides

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Iddq test - PowerPoint PPT Presentation

Lecture 21 I DDQ Current Testing

IDDQ Testing

EE 587 SoC Design &amp; Test

EE 587 SoC Design & Test