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Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures

Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures. Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, Anant Agarwal. Laboratory for Computer Science Massachusetts Institute of Technology. Motivation. As a thought experiment,

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Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures