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How to Speed-up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining

How to Speed-up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. 2 RUAG Space Vienna andreas.dielacher@space.at. 1 Vienna University of Technology Embedded Computing Systems Group { fuegger , s}@ ecs.tuwien.ac.at.

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Lock step case 1 - PowerPoint PPT Presentation

How to Speed-up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining