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Interconnect Optimization for Deep-Submicron and Gigahertz ICs

Interconnect Optimization for Deep-Submicron and Gigahertz ICs. Lei He http://cadlab.cs.ucla.edu/~helei UCLA Computer Science Department Los Angeles, CA 90095. Agenda. Background LR-based STIS optimization LR -- local refinement STIS -- simultaneous transistor and interconnect sizing

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Interconnect Optimization for Deep-Submicron and Gigahertz ICs