Mips memory - PowerPoint PPT Presentation

Digital Logic Design 234262

Digital Logic Design 234262. Alex Bronstein. Lecture 5 : MIPS Instruction Set Architecture. Abstraction Hierarchy. Application Software Operating System ( threads, files, exceptions ) Computer Architecture ( instruction set ) Micro-Architecture ( execution pipeline )

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Decoding MIPS Assembly

Decoding MIPS Assembly. MIPS Memory. MIPS 32 and 64 bit versions 32 bits for Data width Instruction size Address space 2 32 ~ 4 billion addresses. MIPS Memory. 2 32 ~ 4 billion addresses Assigned to bytes 32 bits : 4 GB addressable memory. OS &amp; Memory.

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360 views • 16 slides

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