'Miss penalty' diaporamas de présentation

Chapter 5

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CS252 Graduate Computer Architecture Lecture 17 Memory Systems Continued

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Five Classic Components of a Computer

Five Classic Components of a Computer. Current Topic: Memory. Processor (CPU). Input. Control. Memory. Datapath. Output. What You Will Learn In This Set of Lectures. Memory Hierarchy Memory Technologies Cache Memory Design Virtual Memory. Memory Hierarchy.

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CS151B Computer Systems Architecture Winter 2002 TuTh 2-4pm - 2444 BH

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John Kubiatowicz Electrical Engineering and Computer Sciences University of California, Berkeley

CS252 Graduate Computer Architecture Lecture 15 3+1 Cs of Caching and many ways Cache Optimizations. John Kubiatowicz Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~kubitron/cs252 http://www-inst.eecs.berkeley.edu/~cs252.

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Platform-based Design 5kk70

Platform-based Design 5kk70. Recap on the Memory Hierarchy. Henk Corporaal Eindhoven University of Technology 2009. Topics. Memories: review Memory Hierarchy: why? Basics of caches Measuring cache performance Improving cache performance Framework for memory hierarchies Virtual memory

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COMP 206 Computer Architecture and Implementation Unit 8b: Cache Misses

COMP 206 Computer Architecture and Implementation Unit 8b: Cache Misses. Siddhartha Chatterjee Fall 2000. Cache Performance. Average Access Time. Miss Rate. Miss Penalty. Exploits spatial locality. Increased Miss Penalty & Miss Rate. Fewer blocks: compromises temporal locality.

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Memory Hierarchy II

Memory Hierarchy II. Review: Reducing Misses. 3 Cs: Compulsory, Capacity, Conflict 1. Reduce Misses via Larger Block Size 2. Reduce Misses via Higher Associativity 3. Reducing Misses via Victim Cache 4. Reducing Misses via Pseudo-Associativity

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Virtual Memory: Concepts

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CS136, Advanced Architecture

CS136, Advanced Architecture. Cache and Memory Performance. Outline. 11 Advanced Cache Optimizations Memory Technology and DRAM optimizations. Why More on Memory Hierarchy?. Processor-Memory Performance Gap Growing. Review: 6 Basic Cache Optimizations. Reducing hit time

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Memory Hierarchy

Memory Hierarchy. Faster Access-Lower Cost. Principle of Locality. Programs access small portions of their address space at any instant of time. Two types Temporal locality Item referenced will be referenced again soon Spatial locality

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Caches

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CENG 450 Computer Systems and Architecture Lecture 15

CENG 450 Computer Systems and Architecture Lecture 15. Amirali Baniasadi amirali@ece.uvic.ca. Announcements. Last Quiz scheduled for March 31st. Cache Write Policy: Write Through versus Write Back. Cache read is much easier to handle than cache write:

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Memories: Review

Memories: Review. SRAM: value is stored on a pair of inverting gates very fast but takes up more space than DRAM (4 to 6 transistors) DRAM: value is stored as a charge on capacitor (must be refreshed) very small but slower than SRAM (factor of 5 to 10). Exploiting Memory Hierarchy.

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Adapted from UCB CS252 S01, Revised by Zhao Zhang in IASTATE CPRE 585, 2004

Lecture 14: Hardware Approaches for Cache Optimizations. Cache performance metrics, reduce miss rates, improve hit time, reduce miss penalty. Adapted from UCB CS252 S01, Revised by Zhao Zhang in IASTATE CPRE 585, 2004. Adapted from UCB CS252 S01. Cache Performance Metrics.

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Main Memory Supporting Caches

Main Memory Supporting Caches. Use DRAMs for main memory Fixed width (e.g., 1 word) Connected by fixed-width clocked bus Bus clock is typically slower than CPU clock Example cache block read 1 bus cycle for address transfer 15 bus cycles per DRAM access 1 bus cycle per data transfer

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How will execution time grow with SIZE?

TIME. ?. array fits in cache. SIZE. How will execution time grow with SIZE?. int array[SIZE]; int sum = 0; for (int i = 0 ; i < 200000 ; ++ i) { for (int j = 0 ; j < SIZE ; ++ j) { sum += array[j]; } }. Large and fast.

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