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Multilevel logic - PowerPoint PPT Presentation


ENGG3190 Logic Synthesis “Multi Level Logic” (Part I)

ENGG3190 Logic Synthesis “Multi Level Logic” (Part I)

ENGG3190 Logic Synthesis “Multi Level Logic” (Part I). Winter 2014 S. Areibi School of Engineering University of Guelph. Outline. Multi Level Synthesis: Why? Representations What are we going to Optimize? How to Optimize it ? Logic Transformations The Algebraic Model.

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1.8k views • 157 slides



Lecture 10

Lecture 10

Lecture 10. PLDs ROMs Multilevel logic. Read-only memories (ROMs). Two dimensional array of stored 1s and 0s Input is an address  ROM decodes all possible input addresses Stored row entry is called a "word" ROM output is the decoded word. n address lines. • • •. inputs.

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352 views • 21 slides


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