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Verilog HDL Basic Syntax

Verilog HDL Basic Syntax. Four valued logic system in Verilog. 0: logic low, false , ground 1: logic high , true , power unknown High impedance ， tri-state. Identifier. Begin with A-Z, a-z or _, and letter/number/$/_ follow Which is true or false?

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582 views • 41 slides

.Net Reflection

.Net Reflection. Taipan Tamsare. Overview. Reflection core concepts Exploring metadata Detail information Attributes Building Types at runtime. What is reflection?. Reflection is the feature in .Net, which enables us to get some information about object in runtime.

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334 views • 15 slides

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