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Day5: January 17, 2000 Pipelining ISA Processor Execution

CS184b: Computer Architecture [Single Threaded Architecture: abstractions, quantification, and optimizations]. Day5: January 17, 2000 Pipelining ISA Processor Execution. Today. Pipelined Processor Issue Hazards structural data control (next time) accommodating impact

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RISC vs. CISC

RISC vs. CISC. Rui Wang Tibor Horvath. Towards CISC. Wired logic  microcode control Temptingly easy extensibility Performance tuning HW implementation of some high-level functions Marketing Add successful instructions of competitors “New feature” hype

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378 views • 10 slides

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