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Using Partial Implications for Redundancy Identification and Fault Equivalence

Using Partial Implications for Redundancy Identification and Fault Equivalence

Using Partial Implications for Redundancy Identification and Fault Equivalence. Vishwani D. Agrawal Agere Systems, Murray Hill, New Jersey v a@agere.com http://cm.bell-labs.com/cm/cs/who/va. Talk Outline. Problem statement Background Implication graph Partial implications

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413 views • 26 slides
Built-in Adaptive Test and Calibration of DAC

Built-in Adaptive Test and Calibration of DAC

Built-in Adaptive Test and Calibration of DAC. Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University, Auburn, AL 36849 18 th IEEE North Atlantic Test Workshop 2009. Outline. Overview Previous Work Proposed BIST Scheme Adaptive Self-Calibration of DAC

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368 views • 22 slides
Concurrent Test Generation

Concurrent Test Generation

Vishwani D. Agrawal, vagrawal@eng.auburn.edu Alok S. Doshi, dosias@auburn.edu. Concurrent Test Generation. Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA For more details, see http://www.eng.auburn.edu/~vagrawal. Problem Statement.

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440 views • 19 slides
ELEC 7770 Advanced VLSI Design Spring 2007 Logic Equivalence

ELEC 7770 Advanced VLSI Design Spring 2007 Logic Equivalence

ELEC 7770 Advanced VLSI Design Spring 2007 Logic Equivalence. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07. Equivalence Checking.

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325 views • 18 slides
Timing Analysis

Timing Analysis

Timing Analysis. Chaitanya Bandi. Instructor: Dr. Vishwani D. Agrawal ELEC 7770 Advanced VLSI Design Team Project. Need for Timing Analysis.

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353 views • 15 slides
Weighted Random and Transition Density Patterns for Scan-BIST

Weighted Random and Transition Density Patterns for Scan-BIST

Weighted Random and Transition Density Patterns for Scan-BIST. Farhana Rashid* Vishwani D. Agrawal Auburn University ECE Department, Auburn, Alabama 36849 * Presently with Intel Corp., Austin, Texas 78746. A BIST Architecture. p 1 = Prob {bit = 1}, or TD = Prob {bit makes transition}.

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281 views • 15 slides

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