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ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices. Adders, subtractors, ALUs. Prev…. XOR (2-level, 3-level) Equivalent symbols XNOR Parity Circuits (Odd, even) Daisy chain Tree Comparators Iterative Parallel. Adders/Subtractors. Half Adder

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Combinational Comparators

Output. Å. B)’. A. B. (A . A B. 0. 0. 1. 0. 1. 0. 1. 0. 0. 1. 1. 1. Combinational Comparators. Comparing two binary inputs A, B each n bits for equality (i.e A = B) is a common operation in computers.

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5.8 Exclusive-OR Gates and Parity Circuits

x⊕y=x · y+x · y. x ⊙ y=x · y+x · y. Outputs. Inputs. X Y. x ⊙ y. x⊕y. 0 0 0 1 1 0 1 1. 0 1 1 0 1 0 0 1. Return. Next. 5.8 Exclusive-OR Gates and Parity Circuits. Exclusive-OR(XOR) Gates.

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