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Inde

Scale. Inde. x. 1, 2, 4, 8. Se. gment re. gister. ´. 15. 2. 0. Base. Displacement. +. V. irtual address. 14. 32. Selector. Ef. fecti. v. e address. Se. gmentation. unit. 32. Linear address. P. aging. unit. 32. Ph. ysical address.

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Inde

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  1. Scale Inde x 1, 2, 4, 8 Se gment re gister ´ 15 2 0 Base Displacement + V irtual address 14 32 Selector Ef fecti v e address Se gmentation unit 32 Linear address P aging unit 32 Ph ysical address Figure 11.2. Address generation in the IA-32 architecture.

  2. Step Operation performed Machine instruction 1 S ¬ [ A ] LO AD A 2 S ¬ [ S ] + [ B ] ADDM B 3 S ¬ [ C ] LO AD C 4 S ¬ [ D ] LO AD D  5 S ¬ [ S 1 ] ¤ [ S ] DIV combined DEL 6 S ¬ [ E ] LO AD E 7 S ¬ [ S ] ´ [ F ] MPYM F 8 S ¬ [ G ] LO AD G 9 S ¬ [ S ] + [ H ] ADDM H  10 S ¬ [ S 1 ] ¤ [ S ] DIV combined DEL  11 S ¬ [ S 1 ] + [ S ] ADD  12 S ¬ [ S 1 ] ¤ [ S ] DIV combined DEL 13 W ¬ [ S ] ST OR W (a) Operations to be performed and the necessary machine instructions a + b c ¤ d e ´ f Stack pointer g + h (b) Temporary results stored in the stack after step 9 Figure 11.9. Stack usage in processing the expression w = ( a + b ) ¤ [ c ¤ d + ( e f ) ¤ ( g + h ) ]

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